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LTC2123

2123fb

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APPLICATIONS INFORMATION

If the common mode of the driver is within 1.1V to 1.5V, it

is possible to drive the DEVCLK inputs directly. Otherwise

a transformer or coupling capacitors are needed (Figures

9 and 10). The maximum (peak) voltage of the input signal

should never exceed VDD +0.1V or go below –0.1V.

The ADC sample clock is derived from DEVCLK. For good

performance the sample clock should have a 50% (±5%)

duty cycle. There are two programmable options provided

in the LTC2123 that will ensure a 50% duty cycle sample

clock:

1) An optional DEVCLK divide-by-two circuit is provided

in the clock path to convert a 2X harmonic DEVCLK to

a 50% duty cycle sample clock. The 2X_CLK option is

enabled via SPI register 2, bit 2.

2) If a 2X clock is not available, the clock Duty Cycle

Stabilizer (DCS) circuit may be enabled. When enabled,

the DEVCLK duty cycle can vary from 30% to 70% and

the duty cycle stabilizer will maintain a constant 50%

internal duty cycle. The duty cycle stabilizer is enabled

via SPI register 2, bit 0. If the 2X_CLK option is selected

in the SPI register the Duty Cycle Stabilizer is disabled

regardless of the state of the DCS_en bit.

Forapplicationswherethesamplerateneedstobechanged

quickly and a 2X clock is not available, both the 2X_CLK

and the clock duty cycle stabilizer may be disabled. In this

case, care should be taken to make the DEVCLK a 50%

(±5%) duty cycle.

Overflow Detection

An overflow (OF) is detected when the analog inputs

are either over-ranged or under-ranged. There are two

mechanisms for reporting an OF event:

1) The OF bit is transmitted as part of the serial bit stream

following the LSB of the ADC data.

2) There is a separate LVDS output pair dedicated to early

indication of an OF event. The LVDS OF indicator has a

latency of 6 sample clock cycles. Both ADC OF signals

are multiplexed to one output pair at double data rate.

The Channel A OF signal is active on the first half of

the internal sample clock and the Channel B OF signal

is active on the second half of the cycle.

The LVDS OF indicator is output at standard LVDS levels:

3.5mA output current and a 1.25V output common mode

voltage. An external 100Ω differential termination resistor

is required to function properly. The termination resis-

tor should be located as close as possible to the LVDS

receiver. If used, this LVDS output pair is enabled via SPI

DATA FORMAT

Table 1 shows the relationship between the analog input

voltage, the digital data output bits and the overflow bit.

The output data format is offset binary.

Figure 9. Sinusoidal DEVCLK Drive

LTC2123

VDD

2123 F09

1.2V

10k

100

0.1µF

T1: MACOM

ETC1-1-13

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