LTC2123

39

2123fb

For more information www.linear.com/LTC2123

APPLICATIONS INFORMATION

Register A4: Bank ID (Address 04h)

D7

D6

D5

D4

D3-D0

X

X

X

X

BID[3:0]

Bits 7-4

Unused Bits

Bits 3-0

BID[3:0]

Bank ID. Default value is 0000

BID is defined in JEDS204B 8.3. Provided as an extension to the DID word. It is only used during the transmission of an initial lane

alignment sequence, and does not impact the configuration or functionality of the ADC or serial link

Register A5: Number of Lanes –1 (Address 05h)

D7

D6

D5

D4

D3

D2-D0

X

X

X

X

X

Bits 7-3

Unused Bits

Bits 2-0

L–1[2:0]

The value of L configures the device. It is also transmitted in the Lane Alignment Sequence

001 = 2 Lanes (One Lane per ADC, Default Setting)

011 = 4 Lanes (Two Lanes per ADC)

Register A6: Number of Frames Per Multiframe –1 (Address 06h)

D7

D6

D5

D4-D0

X

X

X

Bits 7-5

Unused Bits

Bits 4-0

Frames Per Multiframe minus 1. Default value is 01111 (16 frames per multiframe)

Register A7: JESD204B Modes (Address 07h)

D7

D6

D5

D4

D3

D2

D1

D0

X

X

LAS_dis

LAM_dis

FAM_dis

0

RST_dis

SCR_en

Bits 7-6

Unused Bits

Bit 5

LAS_dis

0 = Lane Alignment Sequence Enabled (Default Setting)

1 = Lane Alignment Sequence Disabled

Bit 4

LAM_dis

0 = Lane Alignment Monitor Enabled (Default Setting)

1 = Lane Alignment Monitor Disabled

Bit 3

FAM_dis

0 = Frame Alignment Monitor Enabled (Default Setting)

1 = Frame Alignment Monitor Disabled

Bit 2

Reserved bit. Set to 0

Bit 1

RST_dis

0 = In Subclass 1, SYSREF Reset of Dividers is Enabled (Default Setting)

In Subclass 2 SYNC~ Reset of Dividers is Enabled (Default Setting)

1 = In Subclass 1, SYSREF Reset of Dividers is Disabled

In Subclass 2 SYNC~ Reset of Dividers is Disabled

Bit 0

SCR_en

0 = Scrambling is Disabled (Default Setting)

1 = Scrambling is Enabled