2.4GHz 802.11b Zero-IF Transceivers

16

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Programmable Registers

The MAX2820/MAX2821 contain programmable regis-

ters to control various modes of operation for the major

circuit blocks. The registers can be programmed

through the 3-wire SPI/QSPI/MICROWIRE-compatible

serial port. The MAX2820/MAX2821 include five pro-

grammable registers:

1) Block-enable register

2) Synthesizer register

3) Channel frequency register

4) Receiver settings register

5) Transmitter settings register

Each register consists of 16 bits. The four most signifi-

cant bits (MSBs) are the register’s address. The twelve

least significant bits (LSBs) are used for register data.

Table 2 summarizes the register configuration. A

detailed description of each register is provided in

Tables 3–6.

Data is shifted in the MSB first. The data sent to the

MAX2820/MAX2821, in 16-bit words, is framed by CSB.

When CSB is low, the clock is active and data is shifted

with the rising edge of the clock. When CSB transitions

to high, the shift register is latched into the register

selected by the contents of the address bits. Only the

last 16 bits shifted into the MAX2820/MAX2821 are

retained in the shift register. No check is made on the

number of clock pulses. Figure 1 documents the serial

interface timing for the MAX2820/MAX2821.

Power-Up Default States

The MAX2820/MAX2821 provide power-up loading of

default states for each of the registers. The states are

loaded on a VCC_DIG supply voltage transition from 0V

grammed through the serial interface or the power sup-

ply voltage is taken to 0V. The default state of each

register is described in Table 3. Note: Putting the IC in

shutdown mode does not change the contents of the

programming registers.

Block-Enable Register

The block-enable register permits individual control of the

enable state for each major circuit block in the

MAX2820/MAX2821. The actual enable condition of the

circuit block is a logical function of the block-enable bit

setting and other control input states. Table 4 documents

the logical definition of state for each major circuit block.

Synthesizer Register

The synthesizer register (SYNTH) controls the reference

frequency divider and charge-pump current of the PLL.

See Table 5 for a description of the bit settings.

Channel Frequency Register

The channel frequency register (CHANNEL) sets the

RF carrier frequency for the MAX2820/MAX2821. The

channel is programmed as a number from 0 to 99. The

actual frequency is 2400 + channel in MHz. The default

setting is 37 for 2437MHz. See Table 6 for a description

of the bit settings.

Receiver Settings Register

The receive settings register (RECEIVE) controls the

receive filter -3dB corner frequency, RX level detector

midpoint, and VGA DC offset nulling parameters. The

defaults are intended to provide proper operation.

However, the filter frequency and detector can be modi-

fied if desired. Do not reprogram VGA DC offset nulling

parameters. These settings were optimized during devel-

opment. See Table 7 for a description of the bit settings.

Transmitter Settings Register

The transmitter settings register (TRANSMIT) controls

the 4-bit PA bias DAC. The 4 bits correspond to a PA

bias current between 0 and full scale (~300µA). See

Table 8 for the bit settings.

4 ADDRESS BITS

12 DATA BITS

A3

A2

A1

A0

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

REGISTER

NAME

MSB

15

14

13

12

11

10

987

65

4

3

2

LSB

ENABLE

0001

E11

E10

E9

E8

E7

E6

E5

E4

E3

E2

E1

E0

SYNTH

0010

XXXX

PD

ICP

R5

R4

R3

R2

R1

R0

CHANNEL

0011

XXXXX

CF6

CF5

CF4

CF3

CF2

CF1

CF0

RECEIVE

0100

2C2

2C1

2C0

1C2

1C1

1C0

DL1

DL0

SF

BW2

BW1

BW0

TRANSMIT

0101

XXXXXX

XX

PA3

PA2

PA1

PA0

Table 2. Programming Register Definition Summary (Address and Data)

X = Don’t care.