2.4GHz 802.11b Zero-IF Transceivers

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17

REGISTER

ADDRESS

DEFAULT

FUNCTION

ENABLE

0001

000000011110

Block-Enable Control Settings (E)

SYNTH

0010

000001000000

Synthesizer Settings:

• Reference frequency (R)

• Charge-pump current (ICP)

• PLL phase detector (PD)

CHANNEL

0011

000000100101

Channel frequency settings (CF)

RECEIVE

0100

111111010010

Receiver Settings:

• VGA DC offset nulling parameter 1 (1C)

• VGA DC offset nulling parameter 2 (2C)

• -3dB lowpass filter bandwidth (BW)

• Detector midpoint level (DL)

• Special function bit (SF)

TRANSMIT

0101

000000000000

Transmit Settings:

• PA bias (PA)

ADDRESS

DATA BIT

CONTENT DEFAULT

DESCRIPTION AND LOGICAL DEFINITION

D11

E(11)

0

Reserved

D10

E(10)

0

PA Bias-Control Enable (PAB_EN)

• PAB_EN = SHDNB • (E(10) + TX_ON)

D9

E(9)

0

Transmit Baseband Filters Enable (TXFLT_EN)

• TXFLT_EN = SHDNB • (E(9) + TX_ON)

D8

E(8)

0

TX Upconverter + VGA + Driver Amp Enable (TXUVD_EN)

• TXUVD_EN = SHDNB • (E(8) + TX_ON)

D7

E(7)

0

Receive Detector Enable (DET_EN)

• DET_EN = SHDNB • (E(7) + RX_ON)

D6

E(6)

0

RX Downconverter + Filters + AGC Amps Enable (RXDFA_EN)

• RXDFA_EN = SHDNB • (E(6) + RX_ON)

D5

E(5)

0

Receive LNA Enable (RXLNA_EN)

• RXLNA_EN = SHDNB • (E(5) + RX_ON )

D4

E(4)

1

Autotuner Enable (AT_EN)

• AT_EN = SHDNB • (E(4) + RX_ON + TX_ON)

D3

E(3)

1

PLL Charge-Pump Enable (CP_EN)

• CP_EN = SHDNB • E(3)

D2

E(2)

1

PLL Enable (PLL_EN)

• PLL_EN = SHDNB • E(2)

D1

E(1)

1

VCO Enable (VCO_EN)

• VCO_EN = SHDNB • E(1)

0 0 0 1

D0

E(0)

0

Reserved

Table 3. Register Power-Up Default States

Table 4. Block-Enable Register (ENABLE)