IR36021 datasheet(25/41 Pages) IRF

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IR36021

DIGITAL POL BUCK CONTROLLER with I2C AND PMBus

Interface

February 27, 2013 | Rev 3.5

TABLE 9: POWER STATES

Power

State

Mode

Recommended

Current

PS0

Full Power, 2Φ(loop1)

Maximum

PS1

Light Load 1Φ

<20A

PS2

Light Load, 1Φ with Diode

Emulation

<5A

The Power States may be commanded through I2C/PMBus,

or the IR36021 can automatically step through the Power

States based upon the regulator conditions as summarized

in Table 10. Auto Mode is ensued when diode‐emulation is

enabled by setting a flag. It should be noted that to use the

commands (I2C/PMBus), Auto Mode should be disabled.

Furthermore, it is recommended to use the Auto Mode or

phase‐shedding option as much as possible instead or

using the commands.

TABLE 10: POWER STATE ENTRY/EXIT

Auto Mode disabled

Auto Mode

PS1

Entry

a) based on current level if

phase‐shed is enabled

b) via command

c) based on current level

if commanded to PS2

based on the current level if

phase‐shed is enabled

PS1

Exit

a) Command to PS0

b) Command to PS2 if

current level is low

c) Current level to PS0

d) current limit To PS0

fe To PS0 if Vout drops

below a threshold (fc_hth)

a) Current level to PS0

b) Current level to PS2

c) to PS0 if Vout drops below

a threshold (fc_hth)

PS2

Entry

a) Command (if current is

lower than threshold)

Current level in phase‐1a

PS2

Exit

a) Command to PS1

b) Command to PS0

c) Current level To PS1

d) Current limit to PS0

e) To PS0 if Vout drops

below a threshold (le_th)

a) to PS0 if Vout drops below

a threshold (le_th)

b) To PS0 or PS1 based on

current

PHASE SHEDDING / DYNAMIC PHASE CONTROL

(DPC)

The designer can configure the VR to dynamically add or

shed one phase as the load current varies. Phase shedding

(or DPC) reduces the number of phases (Figures 28‐30)

based upon monitoring both filtered total current and

error voltage over the DPC filter window. Monitoring the

error voltage insures that the VR will not drop a phase

during large load oscillations.

Figure 28 shows that at startup, if the load current is below

the 2‐phase current threshold, one phase is dropped

shortly after PGood1 goes high.

Figure 28: Phase Shed 2Φ1Φ at startup

During a large load step for loop1 and based upon the

error voltage, the controller instantly goes to 2‐phase

operation and will remain there for the DPC filter delay

(BW≈40kHz) after which a phase will be dropped

depending on the load current (Figure 29). The error‐

threshold, which should be exceeded, is called ‘L1_fc_hth’.

This threshold is among the ATA settings. The ATA circuitry

ensures that the idle phase is activated with optimum

timing during a load step (this is still valid even if ATA is

disabled).

Figure 30 shows that how adding/dropping a phase is

automatically done based on the current level. For this

figure, the slew‐rate of the load step is not high enough to

make a Vout drop larger than the threshold. Therefore,

phase dropping/adding is delayed because it is based on

the measured load current which is low‐pass filtered.

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