FT232H datasheet(20/65 Pages) FTDI

20 / 65 page

Document No.: FT_000288

FT232H SINGLE CHANNEL HI-SPEED USB TO MULTIPURPOSE UART/FIFO IC

Datasheet Version 1.81

Clearance No.: FTDI #199

3.5.7 FT232H Pins Configured as a CPU-style FIFO Interface

The FT232H can be configured in a CPU-style FIFO interface mode which allows a CPU to interface to USB

via the FT232H. This mode is enabled in the external EEPROM.

When configured in this mode, the pins used and the descriptions of the signals are shown in Table 3.12

Pin No.

Name

Type

Fast Serial Interface Configuration

Description

13, 14, 15, 16,

17, 18, 19, 20

ADBUS[7:0]

I/O

D7 to D0 bidirectional data bus

CS#

INPUT

Active low chip select input

INPUT

Address bit A0

RD#

INPUT

Active Low FIFO Read input

WR#

INPUT

Active Low FIFO Write input

SIWU#

INPUT

Tie this pin to VCCIO if not used – otherwise, for

normal operation

The Send Immediate / WakeUp signal combines two

functions on a single pin. If USB is in suspend mode

(PWREN# = 1) and remote wakeup is enabled in the

EEPROM, strobing this pin low will cause the device to

request a resume on the USB Bus. Normally, this can

be used to wake up the Host PC.

During normal operation (PWREN# = 0), if this pin is

strobed low any data in the device RX buffer will be

sent out over USB on the next Bulk-IN request from

the drivers regardless of the pending packet size. This

can be used to optimize USB transfer speed for some

applications.

Table 3.12 CPU-style FIFO Interface Configured Pin Descriptions

For a functional description of this mode, please refer to section 4.10

FT232H Datasheet(PDF) 20 Page - Future Technology Devices International Ltd.

FT232H Datasheet(HTML) 20 Page - Future Technology Devices International Ltd.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

Datasheet Download

Link URL