FT232H datasheet(36/65 Pages) FTDI

36 / 65 page

Document No.: FT_000288

FT232H SINGLE CHANNEL HI-SPEED USB TO MULTIPURPOSE UART/FIFO IC

Datasheet Version 1.81

Clearance No.: FTDI #199

4.8 MPSSE Interface Mode Description.

MPSSE Mode is designed to allow the FT232H to interface efficiently with synchronous serial protocols

such as JTAG, I2C and SPI (MASTER) Bus. It can also be used to program SRAM based FPGA’s over USB.

The MPSSE interface is designed to be flexible so that it can be configured to allow any synchronous

serial protocol (industry standard or proprietary) to be implemented using the FT232H.

MPSSE is fully configurable, and is programmed by sending commands down the data stream. These can

be sent individually or more efficiently in packets. MPSSE is capable of a maximum sustained data rate of

30 Mbits/s.

When the FT232H is configured in MPSSE mode, the IO timing and signals used are shown in

Figure 4.14 and Table 4.4 These show timings for CLKOUT=30MHz. CLKOUT can be divided internally to

be provide a slower clock.

Figure 4.14 MPSSE Signal Waveforms

Name

Min

Typ

Max

Units

Comments

16.67

15.15

CLKOUT period

7.5

8.33

9.17

CLKOUT high period

7.5

8.33

9.17

CLKOUT low period

7.15

CLKOUT to TDI/DO delay

TDI/DO hold time

TDI/DO setup time

Table 4.4 MPSSE Signal Timings

FT232H Datasheet(PDF) 36 Page - Future Technology Devices International Ltd.