FT900 datasheet(34/58 Pages) FTDI

34 / 58 page

FT900/1/2/3 Embedded Microcontroller Datasheet

Version 1.0

Document No.: FT_000965 Clearance No.: FTDI#421

4.23.1 Features:



All GPIO default to inputs after reset (except GPIO0/1/2).



Multi-function selection on GPIO pins.



Pull-up/Pull-down resistor configuration and open-drain configuration can be

programmed through the pin connect block for each GPIO pin.



Direction control of individual bits.



Supports GPIO input Schmitt trigger to help remove noise.



Supports GPIO interrupt, where each enabled GPIO interrupt can be used to wake-up

the system from power-down mode.

4.24 System Clocks

4.24.1 12 MHz Oscillator

The oscillator generates a 12 MHz reference frequency output to the clock multiplier PLL. The

oscillator clock source comes from either an external 12 MHz crystal or a 12 MHz square wave

clock. The external crystal is connected across XI/CLKIN and XIO in the configuration shown in

Section 6.1. The optional external clock input is connected to XI/CLKIN only.

4.24.2 Phase Locked Loop

The internal PLL takes a 12 MHz clock input from a crystal oscillator. The PLL outputs the 100

MHz system clock frequency to the CPU processor and other peripheral circuits. Each

peripheral has an individual enable control signal to gate the clock source.

4.24.3 32.768 KHz RTC Oscillator

The RTC oscillator provides a clock to the RTC time counter. Either an external 32.768 kHz

crystal or a 32.768 kHz square wave clock can be used as the clock source. The external

crystal is connected across RTC_XI/RTC_CLKIN and RTC_XIO in the configuration shown in

Section 6.2. The optional external clock input is connected to RTC_XI/RTC_CLKIN only.

4.24.4 Internal Slow Clock Oscillator

The internal slow clock oscillator provides at least 5ms slow clock source to generate an

interrupt for the USB2.0 device remote wake-up feature. A USB2.0 device with remote wake-

up capability may not generate resume signalling unless the bus has been continuously in the

idle state for 5ms. The detail description for USB2.0 suspend/resume, please refer to USB2.0

specification chapter7.1.7.7.

4.25 Power Management

4.25.1 Power Supply

The FT900 series may be operated with a single supply of +3.3V apply to VCCIO3V3,

VUSB3V3, VETH3V3 and VCC3V3A pins. The +1.2V internal regulator VOUT1 provides the

power to the core circuit after VCCIO3V3 power on and the system will generate a Power on

Reset (POR) pulse when the output voltage rises above the POR threshold.

The second +1.2V internal regulator VOUT2 will provide the power to the Ethernet transceiver

when VETH3V3 gets the power supply.

FT900 Datasheet(PDF) 34 Page - Future Technology Devices International Ltd.

FT900 Datasheet(HTML) 34 Page - Future Technology Devices International Ltd.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

Datasheet Download

Link URL