S1011 datasheet(9/43 Pages) SII

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HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR

Rev.1.2_00

S-1011 Series

Seiko Instruments Inc.



Electrical Characteristics

1. VDD detection product

1. 1 S-1011 Series J / L type

Table 15

(Ta =

+25°C unless otherwise specified)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Test

Circuit

Detection voltage

−VDET

3.6 V

≤ −VDET(S) ≤ 4.15 V

−VDET(S)

× 0.970

−VDET(S)

× 1.030

4.2 V

≤ −VDET(S) ≤ 4.95 V

−VDET(S)

× 0.975

−VDET(S)

× 1.025

Hysteresis width

VHYS

J type

3.6 V

≤ −VDET(S) ≤ 4.15 V

−VDET

× 0.010

−VDET

× 0.050

−VDET

× 0.100

4.2 V

≤ −VDET(S) ≤ 4.95 V

−VDET

× 0.020

−VDET

× 0.050

−VDET

× 0.090

L type

3.6 V

≤ −VDET(S) ≤ 4.95 V

−

Current consumption

ISS

VDD =

−VDET − 0.1 V, 3.6 V ≤ −VDET ≤ 4.95 V

−

0.60

1.60

μA2

Operation voltage

VDD

−

1.8

−

36.0

Output current

IOUT

Output transistor

Nch

VDS

*3 = 0.05 V

VDD = 2.9 V

0.33

−

Leakage current

ILEAK

Output transistor

Nch

VDD = 30.0 V, VOUT = 30.0 V

−

2.0

μA3

Detection delay time

tRESET

CN = 3.3 nF

8.0

10.0

12.0

Release delay time

tDELAY

CP = 3.3 nF

8.0

10.0

12.0

CP pin discharge

ON resistance

RCP

VDD = 6.9 V, VCP = 0.5 V

0.52

−

2.2

−

CN pin discharge

ON resistance

RCN

VDD = 2.9 V, VCN = 0.5 V

1.0

−

5.0

−

*1.

−VDET: Actual detection voltage value, −VDET(S): Set detection voltage value

*2. Hysteresis width is "unavailable", so release voltage = detection voltage.

*3. VDS: Drain-to-source voltage of the output transistor

*4. The time period from when the pulse voltage of

−VDET(S) + 0.5 V → −VDET(S) − 0.5 V is applied to the VDD pin to when

VOUT reaches VDD / 2, after the power supply voltage (VDD) reaches the release voltage once.

*5. The time period from when the pulse voltage of

−VDET(S) − 0.5 V → −VDET(S) + 0.5 V is applied to the VDD pin to when

VOUT reaches VDD / 2.

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