ISO7340C_15 datasheet(8/34 Pages) TI

8 / 34 page

ISO7340C, ISO7340FC, ISO7341C, ISO7341FC, ISO7342C, ISO7342FC

SLLSEI6E – SEPTEMBER 2014 – REVISED APRIL 2015

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6.6 Switching Characteristics

VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tPLH, tPHL

Propagation delay time

See Figure 13

PWD(1)

Pulse width distortion |tPHL – tPLH|

Same-direction Channels

2.5

tsk(o)

(2)

Channel-to-channel output skew time

Opposite-direction Channels

tsk(pp)

(3)

Part-to-part skew time

Output signal rise time

2.1

See Figure 13

Output signal fall time

1.7

tPHZ

Disable Propagation Delay, high-to-high impedance output

tPLZ

Disable Propagation Delay, low-to-high impedance output

ISO734xC

Enable Propagation Delay, high

tPZH

See Figure 14

impedance-to-high output

ISO734xFC

15000

23000(4)

ISO734xC

15000

23000(4)

Enable Propagation Delay, high

tPZL

impedance-to-low output

ISO734xFC

tfs

Fail-safe output delay time from input power loss

See Figure 15

9.4

μs

(1)

Also known as Pulse Skew.

(2)

tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same

direction while driving identical loads.

(3)

tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same

direction while operating at identical supply voltages, temperature, input signals and loads.

(4)

The enable signal rate should be

≤ 43 Kbps.

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