TSI340 datasheet(21/149 Pages) IDT

21 / 149 page

1. Functional Overview

Tsi340 User Manual

80E3000_MA001_05

Integrated Device Technology

www.idt.com

The following steps detail the memory read flow through the Tsi340:

•

The read request from the initiator is posted/entered into the Non-Posted Queue,

•

The transaction is terminated by signaling target retry to the initiator

•

When the target retry is received, the initiator is required to continue to repeat the same read

transaction until at least one data transfer is completed or until a master/target abort is received

•

The Tsi340 then arbitrates for the destination bus and initiates a read transaction using the exact

read address and read command

— If Tsi340 receives retry on the target bus, it continues to repeat the read transaction until at

least one data transfer is completed, or until an error condition is encountered.

•

When the transaction is completed on the target bus, the Tsi340 transfers the data to the initiator

when the initiator repeats the transaction

1.4.2

Posted Write Transaction Flow

The conventional PCI memory write and memory write and invalidate are posted transactions. Unlike

non-posted transactions these transactions are first completed on the originating bus and then

completed on the destination bus. Figure 4 shows the Tsi340 posted write flow.

When a memory read transaction targets non-prefetchable address space the Tsi340 will

pre-fetch a single DWORD of data when the memory read command is used. For all other

read transactions the Tsi340 will pre-fetch data according to the pre-fetch algorithm, see

“Read Transactions” on page 29.

TSI340 Datasheet(PDF) 21 Page - Integrated Device Technology