TSI340 datasheet(51/149 Pages) IDT

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3. Address Decoding

Tsi340 User Manual

80E3000_MA001_05

Integrated Device Technology

www.idt.com

The prefetchable memory address range has a granularity and alignment of 1 MB. The maximum

memory address range is 4 GB when 32-bit addressing is used, and above 4 GB when 64-bit addressing

is used. The prefetchable memory address range is defined by a 16-bit prefetchable memory base

address register at configuration offset 24h and by a 16-bit prefetchable memory limit address register

at offset 0x26. The top 12 bits of each of these registers correspond to bits <31:20> of the memory

address. The low 4 bits are hardwired to 1h, indicating 64-bit address support. The low 20 bits of the

prefetchable memory base address are assumed to be 0 0000h, which results in a natural alignment to a

1 MB boundary. The low 20 bits of the prefetchable memory limit address are assumed to be 0xFFFFF,

which results in an alignment to the top of a 1 MB block.

To turn off the prefetchable memory address range, write the prefetchable memory base address

value must be greater than the entire limit value, meaning that the upper 32 bits must be considered.

Therefore, to disable the address range, the upper 32 bits registers can both be set to the same value,

while the lower base register is set greater than the lower limit register; otherwise, the upper 32-bit base

must be greater than the upper 32-bit limit.

The initial state of the prefetchable memory base address register is 0x0000 0000. The initial

state of the prefetchable memory limit address register is 0x000F FFFF. Note that the initial

states of these registers define a prefetchable memory range at the bottom 1 MB block of

memory. Write these registers with their appropriate values before setting either the memory

enable bit or the master enable bit in the command register in configuration space.

TSI340 Datasheet(PDF) 51 Page - Integrated Device Technology