TSI340 datasheet(39/149 Pages) IDT

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2. PCI Interface

Tsi340 User Manual

80E3000_MA001_05

Integrated Device Technology

www.idt.com

2.4.1.1

Master Latency Timer Expiration

If Tsi340 is delivering posted write data when it terminates the transaction because the master latency

timer expires, it initiates another transaction to deliver the remaining write data. The address of the

transaction is updated to reflect the address of the current Dword to be delivered. If Tsi340 is

prefetching read data when it terminates the transaction because the master latency timer expires, it

does not repeat the transaction to obtain more data.

2.4.2

Master Abort Received by Tsi340

If Tsi340 initiates a transaction on the target bus and does not detect DEVSEL# returned by the target

within five clock cycles of Tsi340’s assertion of FRAME#, Tsi340 terminates the transaction with a

master abort. Tsi340 sets the received master abort bit in the status register corresponding to the target

bus.

For delayed read and write transactions, when the master abort mode bit in the “Bridge Control

transactions, returns FFFF_FFFFh as data. When the master abort mode bit is 1, Tsi340 returns target

abort on the initiator bus. Tsi340 also sets the signaled target abort bit in the register corresponding to

the initiator bus.

When a master abort is received in response to a posted write transaction, Tsi340 discards the posted

write data and makes no more attempts to deliver the data. Tsi340 sets the received master abort bit in

the status register when the master abort is received on the primary bus, or it sets the received master

abort bit in the secondary status register when the master abort is received on the secondary interface.

When a master abort is detected in response to a posted write transaction, and the master abort mode bit

is set, the Tsi340 also asserts P_SERR_b. The functionality must be enabled by the SERR# enable bit

in the command register and not be disabled by the device-specific P_SERR_b disable bit for master

abort during posted write transactions (that is, master abort mode = 1; SERR# enable bit = 1; and

P_SERR_b disable bit for master aborts = 0.)

2.4.3

Target Termination Received by Tsi340

When Tsi340 initiates a transaction on the target bus and the target responds with DEVSEL#, the target

can end the transaction with one of the following types of termination:

•

Normal termination (upon deassertion of FRAME#)

•

Target retry

•

Target disconnect

•

Target abort

Tsi340 handles these terminations in different ways, depending on the type of transaction being

performed.

When Tsi340 performs a Type 1 to special cycle translation, a master abort is the expected

termination for the special cycle on the target bus. In this case, the master abort received bit is

not set, and the Type 1 configuration transaction is disconnected after the first data phase.

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