TSI340 datasheet(41/149 Pages) IDT

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2. PCI Interface

Tsi340 User Manual

80E3000_MA001_05

Integrated Device Technology

www.idt.com

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Tsi340 makes 2 24 write attempts resulting in a response of target retry

— After Tsi340 makes 2 24 attempts of the same delayed write transaction on the target bus,

Tsi340 asserts P_SERR_b if the primary SERR# enable bit is set in the command register and

the implementation-specific P_SERR_b disable bit for this condition is not set in the

P_SERR_b event disable register. Tsi340 stops initiating transactions in response to that

delayed write transaction. The delayed write request is discarded. Upon a subsequent write

transaction attempt by the initiator, Tsi340 returns a target abort.

2.4.5

Posted Write Target Termination Response

When Tsi340 initiates a posted write transaction, the target termination cannot be passed back to the

initiator. Table 7 shows Tsi340 response to each type of target termination that occurs during a posted

write transaction.

When a target retry or target disconnect is returned and posted write data associated with that

transaction remains in the write buffers, Tsi340 initiates another write transaction to attempt to deliver

the rest of the write data. In the case of a target retry, the same address is driven as for the initial write

transaction attempt. If a target disconnect is received, the address that is driven on a subsequent write

transaction attempt is updated to reflect the address of the current Dword. If the initial write transaction

is a memory write and invalidate transaction, and a partial delivery of write data to the target is

performed before a target disconnect is received, Tsi340 uses the memory write command to deliver

the rest of the write data because less than a cache line will be transferred in the subsequent write

transaction attempt.

After Tsi340 makes 2 24 write transaction attempts and fails to deliver all the posted write data

associated with that transaction, Tsi340 asserts P_SERR_b if the primary SERR# enable bit is set in the

command register and the device-specific P_SERR_b disable bit for this condition is not set in the

P_SERR_b event disable register. The write data is discarded.

Table 7: Tsi340 Response to Posted Write Target Termination

Target Termination

Response

Normal

No additional action.

Target retry

Repeat write transaction to target.

Target disconnect

Initiate write transaction to deliver remaining posted write data.

Target abort

Set received target abort bit in the target interface status register. Assert P_SERR_b if enabled,

and set the signaled system error bit in the primary status register.

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