TSI340 datasheet(34/149 Pages) IDT

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2. PCI Interface

Tsi340 User Manual

80E3000_MA001_05

Integrated Device Technology

www.idt.com

2.3.1

Type 0 Access to Tsi340

Tsi340 configuration space is accessed by a Type 0 configuration transaction on the primary interface.

Tsi340 configuration space cannot be accessed from the secondary bus. Tsi340 responds to a Type 0

configuration transaction by asserting P_DEVSEL_b when the following conditions are met during the

address phase:

•

The bus command is a configuration read or configuration write transaction

•

Low 2 address bits P_AD<1:0> must be 00b

•

Signal P_IDSEL must be asserted.

Tsi340 limits all configuration accesses to a single Dword data transfer and returns a target disconnect

with the first data transfer if additional data phases are requested. Because read transactions to Tsi340

configuration space do not have side effects, all bytes in the requested Dword are returned, regardless

of the value of the byte enable bits.

Type 0 configuration write and read transactions do not use Tsi340 data buffers; that is, these

transactions are completed immediately, regardless of the state of the data buffers.

2.3.2

Type 1 to Type 0 Translation

Type 1 configuration transactions are used specifically for device configuration in a hierarchical PCI

bus system. A PCI-to-PCI bridge, such as the Tsi340, is the only type of device that should respond to

a Type 1 configuration command. Type 1 configuration commands are used when the configuration

access is intended for a PCI device that resides on a PCI bus other than the one where the Type 1

transaction is generated.

Tsi340 performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the primary

bus and is intended for a device attached directly to the secondary bus. Tsi340 must convert the

configuration command to a Type 0 format so that the secondary bus device can respond to it. Type 1 to

Type 0 translations are performed only in the downstream direction; that is, Tsi340 generates a Type 0

transaction only on the secondary bus, and never on the primary bus.

Tsi340 forwards Type 1 to Type 0 configuration read or write transactions as delayed transactions. Type

1 to Type 0 configuration read or write transactions are limited to a single 32-bit data transfer.

2.3.2.1

Address Phase Requirements

Tsi340 responds to a Type 1 configuration transaction and translates it into a Type 0 transaction on the

secondary bus when the following conditions are met during the address phase:

•

The lower two address bits on P_AD<1:0> are 01b.

•

The bus number in address field P_AD<23:16> is equal to the value in the secondary bus number

The function code is ignored because Tsi340 is a single-function device.

Tsi340 ignores all Type 0 transactions initiated on the secondary interface.

TSI340 Datasheet(PDF) 34 Page - Integrated Device Technology

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