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3. Address Decoding

Tsi340 User Manual

80E3000_MA001_05

Integrated Device Technology

www.idt.com

3.4

Memory Address Decoding

Tsi340 has three mechanisms for defining memory address ranges for forwarding of memory

transactions:

•

Memory-mapped I/O base and limit address registers

•

Prefetchable memory base and limit address registers

•

VGA mode

To enable downstream forwarding of memory transactions, the memory enable bit must be set in the

command register in Tsi340 configuration space (see “Primary Command Register—Offset 0x04” on

page 108). To enable upstream forwarding of memory transactions, the master enable bit must be set in

the command register (see “Primary Command Register—Offset 0x04” on page 108). Setting the

master enable bit also allows upstream forwarding of I/O transactions.

3.4.1

Memory-Mapped I/O Base and Limit Address Registers

Memory-mapped I/O is also referred to as non-prefetchable memory. Memory addresses that cannot

automatically be prefetched but that can conditionally prefetch based on command type should be

mapped into this space. Read transactions to non-prefetchable space may exhibit side effects; this space

may have non-memory-like behavior. Tsi340 prefetches in this space only if the memory read line or

memory read multiple commands are used; transactions using the memory read command are limited

to a single data transfer.

The memory-mapped I/O base address and memory-mapped I/O limit address registers define an

address range that Tsi340 uses to determine when to forward memory commands. Tsi340 forwards a

memory transaction from the primary to the secondary interface if the transaction address falls within

the memory-mapped I/O address range. Tsi340 ignores memory transactions initiated on the secondary

interface that fall into this address range. Any transactions that fall outside this address range are

ignored on the primary interface and are forwarded upstream from the secondary interface (provided

that they do not fall into the prefetchable memory range or are not forwarded downstream by the VGA

mechanism).

The memory-mapped I/O range supports 32-bit addressing only. The PCI-to-PCI Bridge Architecture

Specification does not provide for 64-bit addressing in the memory-mapped I/O space. The

memory-mapped I/O address range has a granularity and alignment of 1 MB. The maximum

memory-mapped I/O address range is 4 GB.

If any Tsi340 configuration state affecting memory transaction forwarding is changed by

configuration write operation on the primary bus at the same time that memory transactions

are ongoing on the secondary bus, Tsi340 response to the secondary bus memory transactions

is not predictable.

Configure the memory-mapped I/O base and limit address registers, prefetchable memory

base and limit address registers, and VGA enable bit before setting the memory enable and

master enable bits, and change them subsequently only when the primary and secondary PCI

buses are idle.

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