AM4376 datasheet(124/261 Pages) TI

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VDDS_RTC

(A)

1.8V

RTC_PWRONRSTn

(B)

1.8V

RTC_PMIC_EN

1.8V

VDDS_CLKOUT

1.8V

VDDA3P3V_USB0/1

3.3V

VDD_CORE

(D)

1.1V

VDD_MPU

(D)

1.1V

CLK_32K_RTC

CLK_M_OSC

VDDS_SRAM_CORE_BG, VDDA1P8V_USB0/1

(C)

1.8V

VDDS_DDR

1.2V/1.35V/1.5V

PWRONRSTn

1.8V

(E)

VDDS, VDDSHVx [x=1-11]

VDDS_OSC, VDDA_ADC0/1, VDDS_PLL_DDR,

VDDS_PLL_CORE_LCD, VDDS_PLL_MPU,

VDDS_SRAM_MPU_BB,

AM4376, AM4377, AM4378, AM4379

SPRS851B – JUNE 2014 – REVISED APRIL 2015

www.ti.com

The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is

disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC.

If the internal RTC LDO is disabled, CAP_VDD_RTC should be sourced from an external 1.1-V power supply. If

CAP_VDD_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on

VDD_CORE.

RTC_PWRONRSTn should be asserted for at least 1 ms and can be released before the 32-kHz clock is stable.

These supplies can be ramped together with the VDDS, VDDSHVx [x=1-11], VDDS_CLKOUT supplies if powered

from the same source.

If a USB port is not used, the respective VDDA1P8V_USB may be connected to any 1.8-V power supply and the

respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If a system does not have a 3.3-

V supply, the VDDA3P3V_USB may be connected to ground.

VDD_MPU and VDD_CORE can be supplied from the same power source if OPPs higher than OPP100 are not used.

It is required to hold the PWRONRSTn terminal low until all the supplies have ramped and the input clock

CLK_M_OSC is stable.

Figure 5-5. Power Sequencing with RTC Feature Enabled, All Dual-Voltage IOs Configured as 1.8 V

124

Specifications

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AM4376 Datasheet(PDF) 124 Page - Texas Instruments

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