AM4376 datasheet(127/261 Pages) TI

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VDDS3P3V_IOLDO,

3.3V

VDD_CORE

(C)

1.1V

VDD_MPU

(C)

1.1V

CLK_M_OSC

1.8V

VDDS_DDR

1.2V/1.35V/1.5V

PWRONRSTn

1.8V/3.3V

(E)

VDDS_RTC, VDDS_OSC, VDDA_ADC0/1,

(F)

VDDA3P3V_USB0/1

(A)

VDDSHVx [x=1-11]

VDDS_SRAM_CORE_BG, VDDA1P8V_USB0/1

(B)

VDDS_PLL_MPU, VDDS_SRAM_MPU_BB,

VDDS_PLL_DDR, VDDS_PLL_CORE_LCD,

CAP_VDD_RTC

(D)

AM4376, AM4377, AM4378, AM4379

www.ti.com

SPRS851B – JUNE 2014 – REVISED APRIL 2015

Power source supplying VDDS3P3V_IOLDO should have a supply slew of >100us.

CAP_VDDS1P8V_IOLDO is the 1.8-V output of VDDA3P3V_IOLDO. VDDS, VDDS_CLKOUT terminals are powered

by shorting them to CAP_VDDS1P8V_IOLDO on the board.

If a USB port is not used, the repsective VDDA1P8V_USB may be connected to any 1.8-V power supply and the

respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If a system does not have a 3.3-

V supply, the VDDA3P3V_USB may be connected to ground.

VDD_MPU and VDD_CORE can be supplied from the same power source if OPPs higher than OPP100 are not used.

The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is

disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC.

If the internal RTC LDO is disabled, CAP_VDD_RTC should be sourced from an external 1.1-V power supply. If

CAP_VDD_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on

VDD_CORE.

VDDS_RTC can be ramped independent of other supplies if RTC_PMIC_EN functionality is not required. If

VDDS_RTC is ramped after VDD_CORE when internal RTC LDO is enabled, there might be a small amount of

leakage current on VDD_CORE.

PWRONRSTn input voltage thresholds are not dependent on VDDSHV3 voltage and the terminal is not fail-safe.

PWRONRSTn can accept 1.8-V or 3.3-V input levels when VDDSHV3 is configured as 3.3 V. However,

PWRONRSTn can only accept 1.8 V input levels when VDDSHV3 is configured as 1.8 V. For details on this input

terminal, see Section 5.7.

The PWRONRSTn terminal must be held low until all the supplies have ramped and the input clock CLK_M_OSC is

stable.

Figure 5-8. Simplified Power Sequencing with RTC Feature Disabled, Dual-Voltage IOs Configured as 3.3

Specifications

127

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