AM4376 datasheet(129/261 Pages) TI

129 / 261 page

MPU

PLL

PER

PLL

DDR

PLL

CORE

PLL

EXTDEV

PLL

VDDS_PLL_MPU

VDDS_PLL_CORE_LCD

VDDA1P8V_USB0

VDDS_PLL_DDR

LCD

PLL

AM4376, AM4377, AM4378, AM4379

www.ti.com

SPRS851B – JUNE 2014 – REVISED APRIL 2015

5.12.2 Clock

5.12.2.1 PLLs

5.12.2.1.1 Digital Phase-Locked Loop Power Supply Requirements

The digital phase-locked loop (DPLL) provides all interface clocks and functional clocks to the processor of the

device. The device integrates 6 different DPLLs:

•

Core DPLL

•

Per DPLL

•

Display DPLL

•

DDR DPLL

•

MPU DPLL

•

EXTDEV DPLL

Figure 5-9 illustrates the power supply connectivity implemented in the device. Table 5-12 provides the power

supply requirements for the DPLL.

Figure 5-9. DPLL Power Supply Connectivity

Table 5-12. DPLL Power Supply Requirements

SUPPLY NAME

DESCRIPTION

MIN NOM

MAX

UNIT

VDDA1P8V_USB0

Supply voltage range for USBPHY and PER DPLL, Analog, 1.8V

1.71

1.8

1.89

Max. peak-to-peak supply noise

mV (p-p)

VDDS_PLL_MPU

Supply voltage range for DPLL MPU, Analog

1.71

1.8

1.89

Max. peak-to-peak supply noise

mV (p-p)

VDDS_PLL_CORE_LCD

Supply voltage range for DPLL CORE, EXTDEV, and LCD, Analog

1.71

1.8

1.89

Max. peak-to-peak supply noise

mV (p-p)

VDDS_PLL_DDR

Supply voltage range for DPLL DDR, Analog

1.71

1.8

1.89

Max. peak-to-peak supply noise

mV (p-p)

Specifications

129

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AM4376 Datasheet(PDF) 129 Page - Texas Instruments

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