AM4376 datasheet(133/261 Pages) TI

133 / 261 page

Device

XTALIN

VSS_OSC

XTALOUT

LVCMOS

Digital

Clock

Source

VDDS_OSC

AM4376, AM4377, AM4378, AM4379

www.ti.com

SPRS851B – JUNE 2014 – REVISED APRIL 2015

5.12.2.3.2 OSC0 LVCMOS Digital Clock Source

Figure 5-12 shows the recommended oscillator connections when OSC0 is connected to an LVCMOS square-

wave digital clock source. The LVCMOS clock source is connected to the XTALIN terminal. In this mode of

operation, the XTALOUT terminal should not be used to source any external components. The printed circuit

board design should provide a mechanism to disconnect the XTALOUT terminal from any external components

or signal traces that may couple noise into OSC0 via the XTALOUT terminal.

The XTALIN terminal has a 15 - 40 k

Ω internal pulldown resistor which is enabled when OSC0 is disabled. This

internal resistor prevents the XTALIN terminal from floating to an invalid logic level which may increase leakage

current through the oscillator input buffer.

Figure 5-12. OSC0 LVCMOS Circuit Schematic

Table 5-15. OSC0 LVCMOS Reference Clock Requirements

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

Frequency, LVCMOS reference clock

19.2, 24, 25,

MHz

or 26

f(XTALIN)

Frequency, LVCMOS reference clock stability and tolerance(1)

-50

ppm

tdc(XTALIN)

Duty cycle, LVCMOS reference clock period

tjpp(XTALIN)

Jitter peak-to-peak, LVCMOS reference clock period

-1

tR(XTALIN)

Time, LVCMOS reference clock rise

tF(XTALIN)

Time, LVCMOS reference clock fall

(1)

Initial accuracy, temperature drift, and aging effects should be combined when evaluating a reference clock for this requirement.

Specifications

133

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