AM4376 datasheet(137/261 Pages) TI

137 / 261 page

Device

RTC_XTALIN

RTC_XTALOUT

N/C

VSS_RTC

AM4376, AM4377, AM4378, AM4379

www.ti.com

SPRS851B – JUNE 2014 – REVISED APRIL 2015

Figure 5-16. OSC1 Not Used Schematic

5.12.2.4 Output Clock Specifications

The device has two clock output signals. The CLKOUT1 signal can be configured to output the master oscillator

(CLK_M_OSC), EXTDEV_PLL, 32-kHz, or several other internal clocks. See the device-specific TRM for more

details. The CLKOUT2 signal can be configured to output the OSC1 input clock, which is referred to as the 32K

oscillator (CLK_32K_RTC) in the device-specific technical reference manual, or four other internal clocks. For

more information related to configuring these clock output signals, see the CLKOUT Signals section of the

device-specific technical reference manual.

5.12.2.5 Output Clock Characteristics

5.12.2.5.1 CLKOUT1

The CLKOUT1 signal can be output on the XDMA_EVENT_INTR0 terminal. This terminal connects to one of

seven internal signals via configurable multiplexers. The XDMA_EVENT_INTR0 multiplexer must be configured

for Mode 3 to connect the CLKOUT1 signal to the XDMA_EVENT_INTR0 terminal.

The default reset configuration of the XDMA_EVENT_INTR0 multiplexer is selected by the logic level applied to

the DSS_HSYNC terminal on the rising edge of PWRONRSTn. The XDMA_EVENT_INTR0 multiplexer is

configured to Mode 7 if the DSS_HSYNC terminal is low on the rising edge of PWRONRSTn or Mode 3 if the

DSS_HSYNC terminal is high on the rising edge of PWRONRSTn. This allows the CLKOUT1 signal to be output

on the XDMA_EVENT_INTR0 terminal without software intervention. In this mode, the output is held low while

PWRONRSTn is active and begins to toggle after PWRONRSTn is released.

5.12.2.5.2 CLKOUT2

The CLKOUT2 signal can be output on the XDMA_EVENT_INTR1 terminal. This terminal connects to one of

seven internal signals via configurable multiplexers. The XDMA_EVENT_INTR1 multiplexer must be configured

for Mode 3 to connect the CLKOUT2 signal to the XDMA_EVENT_INTR1 terminal.

The default reset configuration of the XDMA_EVENT_INTR1 multiplexer is always Mode 7. Software must

configure the XDMA_EVENT_INTR1 multiplexer to Mode 3 for the CLKOUT2 signal to be output on the

XDMA_EVENT_INTR1 terminal.

5.12.3

Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data manual do not include delays by board routings. As a good

board design practice, such delays must always be taken into account. Timing values may be adjusted by

increasing or decreasing such delays. TI recommends using the available IO buffer information specification

(IBIS) models to analyze the timing characteristics correctly. If needed, external logic hardware such as buffers

may be used to compensate any timing differences.

The timing parameter values specified in this data manual assume the SLEWCTRL bit in each pad control

For the LPDDR2, DDR3, and DDR3L memory interfaces, it is not necessary to use the IBIS models to analyze

timing characteristics. TI provides a PCB routing rules solution that describes the routing rules to ensure the

memory interface timings are met.

Specifications

137

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