AM4376 datasheet(143/261 Pages) TI

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GMII[x]_MRCLK (Input)

GMII[x]_RXD[3:0], GMII[x]_RXDV,

GMII[x]_RXER (Inputs)

GMII[x]_TXCLK

AM4376, AM4377, AM4378, AM4379

www.ti.com

SPRS851B – JUNE 2014 – REVISED APRIL 2015

Table 5-28. Timing Requirements for GMII[x]_TXCLK - MII Mode

(see Figure 5-23)

10 Mbps

100 Mbps

NO.

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

tc(TX_CLK)

Cycle time, TX_CLK

399.96

400.04

39.996

40.004

tw(TX_CLKH)

Pulse Duration, TX_CLK high

140

260

tw(TX_CLKL)

Pulse Duration, TX_CLK low

140

260

tt(TX_CLK)

Transition time, TX_CLK

Figure 5-23. GMII[x]_TXCLK Timing - MII Mode

Table 5-29. Timing Requirements for GMII[x]_RXD[3:0], GMII[x]_RXDV, and GMII[x]_RXER - MII Mode

(see Figure 5-24)

10 Mbps

100 Mbps

NO.

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

tsu(RXD-RX_CLK)

Setup time, RXD[3:0] valid before RX_CLK

tsu(RX_DV-RX_CLK)

Setup time, RX_DV valid before RX_CLK

tsu(RX_ER-RX_CLK)

Setup time, RX_ER valid before RX_CLK

th(RX_CLK-RXD)

Hold time RXD[3:0] valid after RX_CLK

th(RX_CLK-RX_DV)

Hold time RX_DV valid after RX_CLK

th(RX_CLK-RX_ER)

Hold time RX_ER valid after RX_CLK

Figure 5-24. GMII[x]_RXD[3:0], GMII[x]_RXDV, GMII[x]_RXER Timing - MII Mode

Specifications

143

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