AM4376 datasheet(172/261 Pages) TI

172 / 261 page

AM4376, AM4377, AM4378, AM4379

SPRS851B – JUNE 2014 – REVISED APRIL 2015

www.ti.com

5.12.8.2.1.2 DDR3 Device Combinations

Because there are several possible combinations of device counts and single-side or dual-side mounting,

Table 5-50 summarizes the supported device configurations.

Table 5-50. Supported DDR3 Device Combinations

NUMBER OF DDR3 DEVICES

DDR3 DEVICE WIDTH (BITS)

MIRRORED?

DDR3 EMIF WIDTH (BITS)

Y(1)

(1)

DDR3 devices are mirrored when half of the devices are placed on the top of the board and the other half are placed on the bottom of

the board.

5.12.8.2.1.3 DDR3 Interface

5.12.8.2.1.3.1 DDR3 Interface Schematic

The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used.

Figure 5-49 shows the schematic connections for 16-bit interface using one x16 DDR3 device. Figure 5-50

shows the schematic connections for 16-bit interface without using VTT termination for the ADDR_CTRL net class

signals. Figure 5-51 shows the schematic connections for 16-bit interface using two x8 DDR3 devices.

Figure 5-52 shows the schematic connections for 32-bit interface using two x16 DDR3 device and Figure 5-53

shows the schematic connections for 32-bit interface using four x8 DDR3 devices.

When not using all or part of a DDR3 interface, the proper method of handling the unused pins is to tie off the

DDR_DQS[x] pins to the VDDS_DDR supply via a 1-k

Ω resistor and pulling the DDR_DQSn[x] pins to ground via

a 1k-

Ω resistor. This must be done for each byte not used. Although these signals have internal pullup and

pulldown, external pullup and pulldown provide additional protection against external electrical noise causing

activity on the signals. Also, include the 49.9-

Ω pulldown for DDR_VTP. The VDDS_DDR and DDR_VREF power

supply terminals need to be connected to their respective power supplies even if the DDR3 interface is not being

used. All other DDR3 interface pins can be left unconnected. Note that the supported modes for use of the DDR3

EMIF are 32 bits wide, 16 bits wide, or not used.

The device can only source one load connected to the DQS[x] and DQ[x] net class signals and up to four loads

connected to the CK and ADDR_CTRL net class signals. For more information related to net classes, see

Section 5.12.8.2.1.3.9.

172

Specifications

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AM4376 Datasheet(PDF) 172 Page - Texas Instruments