AM4376 datasheet(171/261 Pages) TI

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DDR_CK

DDR_CKn

AM4376, AM4377, AM4378, AM4379

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SPRS851B – JUNE 2014 – REVISED APRIL 2015

5.12.8.2 Memory Interface

The device has a dedicated interface to LPDDR2, DDR3, and DDR3L SDRAM. It supports JEDEC standard

compliant LPDDR2, DDR3, and DDR3L SDRAM devices with a 16- or 32-bit data path to external SDRAM

memory.

For more details on the LPDDR2, DDR3, and DDR3L memory interface, see the EMIF section of the AM437x

Sitara Processors Technical Reference Manual (SPRUHL7).

5.12.8.2.1 DDR3 and DDR3L Routing Guidelines

This section provides the timing specification for the DDR3 and DDR3L interface as a PCB design and

manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity,

cross-talk, and signal timing. These rules, when followed, result in a reliable DDR3 or DDR3L memory system

without the need for a complex timing closure process. For more information regarding the guidelines, see the

Understanding TI’s PCB Routing Rule-Based DDR Timing Specification application report (literature number

SPRAAV0). This application report provides generic guidelines and approach. All the specifications provided in

the data manual take precedence over the generic guidelines and must be adhered to for a reliable DDR3 or

DDR3L interface operation.

NOTE

All references to DDR3 in this section apply to DDR3 and DDR3L devices, unless otherwise noted.

5.12.8.2.1.1 Board Designs

TI only supports board designs using DDR3 memory that follow the guidelines in this document. The switching

characteristics and timing diagram for the DDR3 memory interface are shown in Table 5-49 and Figure 5-48.

Table 5-49. Switching Characteristics for DDR3 Memory Interface

NO.

PARAMETER

MIN

MAX

UNIT

tc(DDR_CK)

Cycle time, DDR_CK and DDR_CKn

2.5

3.3(1)

tc(DDR_CKn)

(1) The JEDEC JESD79-3F Standard defines the maximum clock period of 3.3 ns for all standard-speed bin DDR3 and DDR3L memory

devices. Therefore, all standard-speed bin DDR3 and DDR3L memory devices are required to operate at 303 MHz.

Figure 5-48. DDR3 Memory Interface Clock Timing

Specifications

171

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