AM5728 datasheet(119/415 Pages) TI

119 / 415 page

AM5728, AM5726

www.ti.com

SPRS915O – MARCH 2014 – REVISED OCTOBER 2015

Table 4-7. EMIF Signal Descriptions (continued)

SIGNAL NAME

DESCRIPTION

TYPE

BALL

ddr1_d2

EMIF1 Data Bus

I/O

AG26

ddr1_d3

EMIF1 Data Bus

I/O

AH26

ddr1_d4

EMIF1 Data Bus

I/O

AF24

ddr1_d5

EMIF1 Data Bus

I/O

AE24

ddr1_d6

EMIF1 Data Bus

I/O

AF23

ddr1_d7

EMIF1 Data Bus

I/O

AE23

ddr1_d8

EMIF1 Data Bus

I/O

AC23

ddr1_d9

EMIF1 Data Bus

I/O

AF27

ddr1_d10

EMIF1 Data Bus

I/O

AG27

ddr1_d11

EMIF1 Data Bus

I/O

AF28

ddr1_d12

EMIF1 Data Bus

I/O

AE26

ddr1_d13

EMIF1 Data Bus

I/O

AC25

ddr1_d14

EMIF1 Data Bus

I/O

AC24

ddr1_d15

EMIF1 Data Bus

I/O

AD25

ddr1_d16

EMIF1 Data Bus

I/O

V20

ddr1_d17

EMIF1 Data Bus

I/O

W20

ddr1_d18

EMIF1 Data Bus

I/O

AB28

ddr1_d19

EMIF1 Data Bus

I/O

AC28

ddr1_d20

EMIF1 Data Bus

I/O

AC27

ddr1_d21

EMIF1 Data Bus

I/O

Y19

ddr1_d22

EMIF1 Data Bus

I/O

AB27

ddr1_d23

EMIF1 Data Bus

I/O

Y20

ddr1_d24

EMIF1 Data Bus

I/O

AA23

ddr1_d25

EMIF1 Data Bus

I/O

Y22

ddr1_d26

EMIF1 Data Bus

I/O

Y23

ddr1_d27

EMIF1 Data Bus

I/O

AA24

ddr1_d28

EMIF1 Data Bus

I/O

Y24

ddr1_d29

EMIF1 Data Bus

I/O

AA26

ddr1_d30

EMIF1 Data Bus

I/O

AA25

ddr1_d31

EMIF1 Data Bus

I/O

AA28

ddr1_ecc_d0

EMIF1 ECC Data Bus

I/O

W22

ddr1_ecc_d1

EMIF1 ECC Data Bus

I/O

V23

ddr1_ecc_d2

EMIF1 ECC Data Bus

I/O

W19

ddr1_ecc_d3

EMIF1 ECC Data Bus

I/O

W23

ddr1_ecc_d4

EMIF1 ECC Data Bus

I/O

Y25

ddr1_ecc_d5

EMIF1 ECC Data Bus

I/O

V24

ddr1_ecc_d6

EMIF1 ECC Data Bus

I/O

V25

ddr1_ecc_d7

EMIF1 ECC Data Bus

I/O

Y26

ddr1_dqm0

EMIF1 Data Mask outputs

AD23

ddr1_dqm1

EMIF1 Data Mask outputs

AB23

ddr1_dqm2

EMIF1 Data Mask outputs

AC26

ddr1_dqm3

EMIF1 Data Mask outputs

AA27

ddr1_dqm_ecc

EMIF1 ECC Data Mask outputs

V26

ddr1_dqs0

Data strobe 0 input/outputs for byte 0 of the 32-bit data bus. These signals are outputs

I/O

AH25

to the EMIF1 memory when writing and inputs when reading.

ddr1_dqsn0

Data strobe 0 invert

I/O

AG25

ddr1_dqs1

Data strobe 1 input/outputs for byte 1 of the 32-bit data bus. These signals are outputs

I/O

AE27

to the EMIF1 memory when writing and inputs when reading.

Terminal Configuration and Functions

119

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