AM5728 datasheet(182/415 Pages) TI

182 / 415 page

AM5728, AM5726

SPRS915O – MARCH 2014 – REVISED OCTOBER 2015

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Table 5-9. Maximum Supported Frequency (continued)

Module

Clock Sources

Clock

Max. Clock

PLL / OSC / Source

PLL / OSC /

Instance Name

Input Clock Name

PRCM Clock Name

Type

Allowed (MHz)

Clock Name

Source Name

WD_TIMER2

WD_TIMER2_ICLK

Int

38.4

WKUPAON_GICLK

SYS_CLK1

OSC1

DPLL_ABE_X2_CLK

DPLL_ABE

WD_TIMER2_FCL

Func

0.032

WKUPAON_SYS_GFC

WKUPAON_32K_GFCL

RTC Oscillator

5.6

Electrical Characteristics

NOTE

The data specified in Section 5.6.1 through Section 5.6.12 are subject to change.

NOTE

The interfaces or signals described in Section 5.6.1 through Section 5.6.12 correspond to the

interfaces or signals available in multiplexing mode 0 (Function 1).

All interfaces or signals multiplexed on the balls described in these tables have the same DC

electrical characteristics, unless multiplexing involves a PHY/GPIO combination in which

case different DC electrical characteristics are specified for the different multiplexing modes

(Functions).

5.6.1

LVCMOS DDR DC Electrical Characteristics

Table 5-10 summarizes the DC electrical characteristics for LVCMOS DDR Buffers.

NOTE

For more information on the I/O cell configurations (i[2:0], sr[1:0]), see the Chapter Control

Module of the Device TRM.

182

Specifications

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