DM385 datasheet(154/281 Pages) TI

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x2M

Multiplier

REFCLK

DCOCLK

CLKOUT

DEV Clock

(

N +

( 2 1)

N +

DEV/AUX

Clock

Multiplier

REFCLK

CLKDCO

CLKOUT

(

N +

( 2 1)

N +

DM385, DM388

SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

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7.4.6

PLLs

The device contains 10 top-level PLLs, and embedded PLLs (within the ARM Cortex-A8, PCIE, and CSI)

that provide clocks to different parts of the system. Figure 7-17 and Figure 7-18 show simplified block

diagrams of the Top-Level PLL and PLL_ARM. In addition, see the System Clocking Overview (Figure 7-

7) for a high-level view of the device clock architecture including the PLL reference clock sources and

connections.

Figure 7-17. Top-Level PLL Simplified Block Diagram

Figure 7-18. PLL_ARM Simplified Block Diagram

The reference clock for most of the PLLs comes from the DEV input clock, with select PLLs also having

the option to use the AUX input clock as a reference. Also, each PLL supports a Bypass mode in which

the reference clock can be directly passed to the PLL CLKOUT through a divider. All device PLL’s will

come-up in Bypass mode after reset.

For details on programming the device PLLs, see the Control Module chapter in the device-specific

Technical Reference Manual.

7.4.6.1

PLL Power Supply Filtering

The device PLLs are supplied externally via the VDDA_xPLL_1P8 power-supply pins (where "x"

represents ARM, VID0, VID1, AUDIO, DDR, and/or L3). External filtering must be added on the PLL

supply pins to ensure that the requirements in Table 7-18 are met.

Table 7-18. PLL Power Supply Requirements

PARAMETER

MIN

MAX

UNIT

Dynamic noise at VDDA_xPLL_1P8 pins

mV p-p

7.4.6.2

PLL Multipliers and Dividers

The Top-Level and PLL_ARM PLLs support the internal multiplier and divider values shown in Table 7-19,

Top-Level PLL Multiplier and Divider Limits and Table 7-20, PLL_ARM Multiplier and Divider Limits. The

PLLs must be programmed to conform to the various REFCLK, CLKDCO, DCOCLK, and CLKOUT limits

described in Section 7.4.6.3, PLL Frequency Limits.

Table 7-19. Top-Level PLL Multiplier and Divider Limits

PARAMETER

MIN

MAX

N Pre-Divider

255

154

Power, Reset, Clocking, and Interrupts

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