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DM385 Datasheet(PDF) 159 Page - Texas Instruments |
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DM385 Datasheet(HTML) 159 Page - Texas Instruments |
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159 / 281 page ![]() DM385, DM388 www.ti.com SPRS821D – MARCH 2013 – REVISED DECEMBER 2013 7.5 Interrupts The device has a large number of interrupts to service the needs of its many peripherals and subsystems. The ARM Cortex-A8 and Media Controller are capable of servicing these interrupts. The following sections list the device interrupt mapping and multiplexing schemes. 7.5.1 ARM Cortex-A8 Interrupts The ARM Cortex-A8 Interrupt Controller (AINTC) is responsible for prioritizing all service requests from the System peripherals and generating either IRQs or FIQs to the Cortex-A8. The AINTC has the capability to handle up to 128 requests, and the priority of the interrupt inputs are programmable. Table 7-26 lists the interrupt sources for the AINTC. For more details on ARM Cortex-A8 interrupt control, see the Interrupt Controller section of the Chip Level Resources chapter in the device-specific Technical Reference Manual. Table 7-26. ARM Cortex-A8 Interrupt Controller (AINTC) Interrupt Sources Cortex-A8 ACRONYM SOURCE INTERRUPT NUMBER 0 EMUINT Cortex-A8 Emulation 1 COMMTX Cortex-A8 Emulation 2 COMMRX Cortex-A8 Emulation 3 BENCH Cortex-A8 Emulation 4 ELM_IRQ ELM 5 – Reserved 6 – Reserved 7 NMI NMIn Pin 8 – Reserved 9 L3DEBUG L3 Interconnect 10 L3APPINT L3 Interconnect 11 TINT8 TIMER8 12 EDMACOMPINT EDMA CC Completion 13 EDMAMPERR EDMA Memory Protection Error 14 EDMAERRINT EDMA CC Error 15 WDTINT0 Watchdog Timer 0 16 – Reserved 17 USBSSINT USB Subsystem 18 USBINT0 USB0 19 USBINT1 USB1 20-27 – Reserved 28 SDINT1 MMC/SD1 29 SDINT2 MMC/SD2 30 I2CINT2 I2C2 31 I2CINT3 I2C3 32 GPIOINT2A GPIO2 A 33 GPIOINT2B GPIO2 B 34 USBWAKEUP USB Subsystem Wakeup 35 PCIeWAKEUP PCIe Wakeup 36 DSSINT HDVPSS 37 – Reserved 38 HDMIINT HDMI 39 ISS_IRQ_5 ISS Copyright © 2013, Texas Instruments Incorporated Power, Reset, Clocking, and Interrupts 159 Submit Documentation Feedback Product Folder Links: DM385 DM388 |
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