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LM49350RLEVAL Datasheet(PDF) 78 Page - Texas Instruments |
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LM49350RLEVAL Datasheet(HTML) 78 Page - Texas Instruments |
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78 / 108 page ![]() LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com DAC Effects Registers Table 67. DAC_ALC_1 (0xA0h) Bits Field Description 2:0 SAMPLE_ RATE This programs the timers on the ALC with the closest DAC sample rate. SAMPLE_ RATE DAC Fs 000 8kHz 001 12kHz 010 16kHz 011 24kHz 100 32kHz 101 48kHz 110 96kHz 111 192kHz 3 LIMITER If set, the circuit will never apply gain to the signal, no matter how small, but it will attenuate the signal as soon as it reaches target and release it at the decay rate, once signal level reduces below target. The I2C gain setting (at the time the LIMITER is enabled) is the maximum gain that the ALC will apply. Care should be taken when choosing the optimum I2C gain setting whenever enabling the Limiter. 4 STEREO LINK If set, the ALC circuit uses the stereo average of the input signals to control the gain of the stereo output. This maintains stereo imaging. If this bit is cleared, then both channels operate as dual mono. Table 68. DAC_ALC_2 (0xA1h) Bits Field Description 3:0 NOISE_FLOOR This sets the anticipated noise floor. Signals lower than the specified noise floor will be gated from the ALC to avoid noise pumping. NOISE_FLOOR Noise Floor (dB) 0000 -39 0001 -42 0010 -45 0011 -48 0100 -51 0101 -54 0110 -57 0111 -60 1000 -63 1001 -66 1010 -69 1011 -72 1100 -75 1101 -78 1110 -81 1111 -84 4 NG_ENB This enables the Noise Gate 78 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Links: LM49350 LM49350RLEVAL |
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