DATA1, DATA2,

DATA3, DATA4

1.4 V

1.4 V

1.4 V

BCK

LRCK

T0010-04

OVERSAMPLING RATE CONTROL

ZERO FLAG

PCM1680

PARAMETER

MIN

UNIT

BCK pulse cycle time

(1)

BCK pulse duration, HIGH

35

ns

BCK pulse duration, LOW

35

ns

LRCK setup time to BCK rising edge

10

ns

LRCK hold time to BCK rising edge

10

ns

DATA1, DATA2, DATA3, DATA4 setup time

10

ns

DATA1, DATA2, DATA3, DATA4 hold time

10

ns

Figure 23. Audio Interface Timing

The PCM1680 automatically controls the oversampling rate of the delta-sigma DACs using the system clock

The PCM1680 has two zero-flag pins, ZERO1 (pin 1) and ZERO2 (pin 28), which are assigned to the

combinations A through D as shown in Table 3. Zero-flag combinations are selected using the zero-flag

combination bits, AZRO[1:0], located in control register 13 of the PCM1680. If the input data of the L-channel

and/or R-channel of all assigned channels remain at a logic-0 level for 1024 sampling periods (LRCK clock

periods), ZERO1 and ZERO2 are set to a logic-1 state, or high level. If the input data of any of the assigned

channels contain a logic-1, ZERO1, and ZERO2 are set to a logic-0 state immediately.

The active polarity of the zero-flag output can be inverted by setting the ZREV bit of control register 10 to 1. The

reset default is active-high output or ZREV = 0.

Table 3. Zero-Flag Output Combinations

ZERO-FLAG COMBINATION

ZERO1 (PIN 1)

ZERO2 (PIN 28)

A

DATA1 L-ch

DATA1 R-ch

B

N/A

DATA[1:4]

C

DATA4

DATA[1:3]

D

DATA1

DATA[2:4]

16

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