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LM5017 Datasheet(PDF) 3 Page - Texas Instruments |
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LM5017 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 31 page ![]() SW BST VCC FB 8 7 6 5 1 2 3 4 UVLO RON RTN VIN WSON-8 Exp Pad UVLO 3 RON 4 RTN 1 VIN 2 8 SW 7 BST 6 VCC 5 FB SO PowePAD-8 Exp Pad LM5017 www.ti.com SNVS783I – JANUARY 2012 – REVISED OCTOBER 2015 5 Pin Configuration and Functions 8-Pin SO PowerPAD DDA Package Top View 8-Pin WSON NGU Package Top View Pin Functions PIN I/O DESCRIPTION APPLICATION INFORMATION NO. NAME 1 RTN — Ground Ground connection of the integrated circuit. 2 VIN I Input Voltage Operating input range is 7.5 V to 100 V. Resistor divider from VIN to UVLO to GND programs the undervoltage detection threshold. An internal current source is Input Pin of Undervoltage 3 UVLO I enabled when UVLO is above 1.225 V to provide hysteresis. When Comparator UVLO pin is pulled below 0.66 V externally, the regulator is in shutdown mode. A resistor between this pin and VIN sets the buck switch on-time as 4 RON I On-Time Control a function of VIN. Minimum recommended on-time is 100 ns at max input voltage. This pin is connected to the inverting input of the internal regulation 5 FB I Feedback comparator. The regulation level is 1.225 V. Output from the Internal High The internal VCC regulator provides bias supply for the gate drivers 6 VCC O Voltage Series Pass Regulator. and other internal circuitry. A 1.0 μF decoupling capacitor is Regulated at 7.6 V recommended. An external capacitor is required between the BST and SW pins 7 BST I Bootstrap Capacitor (0.01- μF ceramic). The BST pin capacitor is charged by the VCC regulator through an internal diode when the SW pin is low. Power switching node. Connect to the output inductor and 8 SW O Switching Node bootstrap capacitor. Exposed pad must be connected to the RTN pin. Solder to the EP — Exposed Pad system ground plane on application board for reduced thermal resistance. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM5017 |
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