LM5019 datasheet(12/30 Pages) TI

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RFB1 x RFB2

RFB1 + RFB2

tS = C1 x (R2 +

)

RFB1 x RFB2

R2 x (RFB1 + RFB2) + RFB1 x RFB2

VFB = (VCC - VD) x

ûIL(MIN)

25 mV

Csw(RFB2||RFB1)

C >

Cr = 3300 pF

RrCr <

Cac = 100 nF

(VIN(MIN) - VOUT) x TON

25 mV

ûIL(MIN)

VOUT

VREF

GND

To FB

COUT

RFB2

RFB1

VOUT

GND

To FB

COUT

RFB2

RFB1

VOUT

Cac

OUT

VOUT

GND

Cac

To FB

RFB2

RFB1

LM5019

SNVS788F – JANUARY 2012 – REVISED DECEMBER 2014

www.ti.com

Feature Description (continued)

The capacitive ripple is not in phase with the inductor current. As a result, the capacitive ripple does not

decrease monotonically during the off-time. The resistive ripple is in phase with the inductor current and

decreases monotonically during the off-time. The resistive ripple must exceed the capacitive ripple at the output

node (VOUT) for stable operation. If this condition is not satisfied unstable switching behavior is observed in COT

converters, with multiple on-time bursts in close succession followed by a long off-time.

Type 3 ripple method uses Rr and Cr and the switch node (SW) voltage to generate a triangular ramp. This

triangular ramp is ac coupled using Cac to the feedback node (FB). Since this circuit does not use the output

voltage ripple, it is ideally suited for applications where low output voltage ripple is required. See AN-1481

Controlling Output Ripple and Achieving ESR Independence in Constant On-Time (COT) Regulator Designs

(SNVA166) for more details for each ripple generation method.

Table 1. Ripple Configuration

TYPE 1

TYPE 2

TYPE 3

LOWEST COST CONFIGURATION

REDUCED RIPPLE CONFIGURATION

MINIMUM RIPPLE CONFIGURATION

7.3.12 Soft-Start

A soft-start feature can be implemented with the LM5019 using an external circuit. As shown in Figure 12, the

soft-start circuit consists of one capacitor, C1, two resistors, R1 and R2, and a diode, D. During the initial start-up,

the VCC voltage is established prior to the VOUT voltage. Capacitor C1 is discharged and D is thereby forward

biased. The FB voltage exceeds the reference voltage (1.225 V) and switching is therefore disabled. As capacitor

C1 charges, the voltage at node B gradually decreases and switching commences. VOUT will gradually rise to

maintain the FB voltage at the reference voltage. Once the voltage at node B is less than a diode drop above the

FB voltage, the soft-start sequence is finished and D is reverse biased.

During the initial part of the start-up, the FB voltage can be approximated as follows. Please note that the effect

of R1 has been ignored to simplify the calculation shown in .

C1 is charged after the first start up. Diode D1 is optional and can be added to discharge C1 and initialize the

soft-start sequence when the input voltage experiences a momentary drop.

To achieve the desired soft-start, the following design guidance is recommended:

(1) R2 is selected so that VFB is higher than 1.225 V for a VCC of 4.5 V, but is lower than 5 V when VCC is 8.55 V.

If an external VCC is used, VFB should not exceed 5 V at maximum VCC.

(2) C1 is selected to achieve the desired start-up time that can be determined as shown in .

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