Pin Function Descriptions

www.onsemi.com

AX5042

7

3.

Pin Function Descriptions

Symbol

Pin(s)

Type

Description

NC

1

N

Not to be connected

VDD

2

P

Power supply

GND

3

G

Ground

ANTP

4

A

Antenna input/output

ANTN

5

A

Antenna input/output

GND

6

P

Ground

VDD

7

P

Power supply

NC

8

N

Not to be connected

LPFILT

9

A

Pin for optional external synthesizer loop filter; leave unconnected if not used

It is recommended to use the internal loop filter

NC

10

N

Not to be connected

GND

11

P

Ground

RESET_N

12

I

Optional reset input. If not used this pin must be connected to VDD.

SYSCLK

13

I/O

Default functionality: Crystal oscillator (or divided) clock output

Can be programmed to be used as a general purpose I/O pin

SEL

14

I

Serial peripheral interface select

CLK

15

I

Serial peripheral interface clock

MISO

16

O

Serial peripheral interface data output

MOSI

17

I

Serial peripheral interface data input

DATA

18

I/O

In wire mode: Data input/output

Can be programmed to be used as a general purpose I/O pin

IRQ_TXEN

19

I/O

In frame mode: Interrupt request output

In wire mode: Transmit enable input

Can be programmed to be used as a general purpose I/O pin

VDD

20

P

Power supply

DCLK

21

I/O

In wire mode: Clock output

Can be programmed to be used as a general purpose I/O pin

GND

22

P

Ground

PWRUP

23

I/O

Power-up/-down input; activates/deactivates analog blocks

Can be programmed to be used as a general purpose I/O pin

If the power-up/-down functionality is handled in software and no usage as

general purpose I/O pin is planned then this pin should be tied to VDD

NC

24

N

Not to be connected

NC

25

N

Not to be connected

VDD

26

P

Power supply

CLK16P

27

A

Crystal oscillator input/output

CLK16N

28

A

Crystal oscillator input/output

A = analog signal

I/O

= digital input/output signal

I

= digital input signal

N

= not to be connected

O =

digital output signal

P

= power or ground

All digital inputs are Schmitt trigger inputs, digital input and output levels are LVCMOS/LVTTL compatible and 3.3V/5V

tolerant

.

The centre pad of the QFN28 package should be connected to GND.