AX5042 datasheet(18/42 Pages) ONSEMI

18 / 42 page

Circuit Description

www.onsemi.com

AX5042

Circuit Description

The AX5042 is a true single chip low-power CMOS transceiver primarily for use in SRD bands.

The on-chip transceiver consists of a fully integrated RF front-end with modulator and

demodulator. Base band data processing is implemented in an advanced and flexible

communication controller that enables user friendly communication via the SPI interface or in

direct wire mode.

AX5042 can be operated from 2.3 V to 2.8 V power supply over a temperature range from

-40°C to 85°C, it consumes 13 - 37 mA for transmitting depending on data mode and output

power and 17 - 23 mA for receiving.

The AX5042 features make it an ideal interface for integration into various battery powered

SRD solutions such as ticketing or as transceiver for telemetric applications e.g. in sensors. As

primary application, the transceiver is intended for UHF radio equipment in accordance with

the European Telecommunication Standard Institute (ETSI) specification EN 300 220-1 and the

US Federal Communications Commission (FCC) standard CFR47, part 15. The use of AX5042 in

accordance to FCC Par 15.247, allows for improved range in the 915 MHz band. Additionally

AX5042 is compatible with the low frequency standards of 802.15.4 (ZigBee).

The AX5042 can be operated in two fundamentally different modes.

In wire mode the IC behaves as an extension of any wire. The internal communication

controller is disabled and the modem data is directly available on a dedicated pin (DATA).

The bit clock is also output on a dedicated pin (DCLK). In this mode the user can connect the

data pin to any port of a micro-controller or to a UART, but has to control coding, checksums,

pre and post ambles. The user can choose between synchronous and asynchronous wire

mode, asynchronous wire mode performs RS232 start bit recognition and re-synchronization

for transmit.

In frame mode data is sent and received via the SPI port in frames. Pre- and postambles as

well as checksums can be generated automatically. Interrupts control the data flow

between a micro-controller and the AX5042.

Both modes can be used both for transmit and receive. In both cases the AX5042 behaves

as a SPI slave interface. Configuration of the AX5042 is always done via the SPI interface.

AX5042 supports any data rate from 1.2 kbps to 250 kbps for FSK, GFSK, GMSK , MSK and from

2 kbps to 600 kbps for ASK and PSK. To achieve optimum performance for specific data rates

and modulation schemes several register settings to configure the AX5042 are necessary,

they are outlined in the following, for details see the AX5042 Programming Manual.

Spreading and despreading is possible on all data rates and modulation schemes. The net

transfer rate is reduced by a factor of 15 in this case. For 802.15.4 either 600 or 300 kbps

modes have to be chosen.

The receiver supports multi-channel operation for all data rates and modulation schemes.

AX5042 Datasheet(PDF) 18 Page - ON Semiconductor