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AX5051 Datasheet(PDF) 18 Page - ON Semiconductor |
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AX5051 Datasheet(HTML) 18 Page - ON Semiconductor |
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18 / 44 page ![]() Specifications www.onsemi.com AX5051 18 SPI Timing SYMBOL DESCRIPTION CONDITION MIN. TYP. MAX. UNIT Tss SEL falling edge to CLK rising edge 10 ns Tsh CLK falling edge to SEL rising edge 10 ns Tssd SEL falling edge to MISO driving 0 10 ns Tssz SEL rising edge to MISO high-Z 0 10 ns Ts MOSI setup time 10 ns Th MOSI hold time 10 ns Tco CLK falling edge to MISO output 10 ns Tck CLK period Note 1 50 ns Tcl CLK low duration 40 ns Tch CLK high duration 40 ns Notes 1. For SPI access during power-down mode the period should be relaxed to 100ns. For a figure showing the SPI timing parameters see section 5.15: Serial Peripheral Interface (SPI). |
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