AX5051 datasheet(32/44 Pages) ONSEMI

32 / 44 page

Circuit Description

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AX5051

5.15. Serial Peripheral Interface (SPI)

The AX5051 can be programmed via a four wire serial interface according SPI using the

pins CLK, MOSI, MISO and SEL. Registers for setting up the AX5051 are programmed

via the serial peripheral interface in all device modes.

When the interface signal SEL is pulled low, a 16-bit configuration data stream is

expected on the input signal pin MOSI, which is interpreted as

D0...D7, A0...A6, R_N/W.

Data read from the interface appears on MISO.

Figure 3 shows a write/read access to the interface. The data stream is built of an

address byte including read/write information and a data byte. Depending on the

R_N/W

bit and address bits

A[6..0], data D[7..0] can be written via MOSI or read at the pin MISO.

R_N/W = 0 means read mode, R_N/W = 1 means write mode.

The read sequence starts with 7 bits of status information

S[6..0] followed by 8 data bits.

The status bits contain the following information:

PLL LOCK

FIFO OVER

FIFO UNDER

FIFO FULL

FIFO EMPTY

FIFOSTAT(1)

FIFOSTAT(0)

SPI Timing

Tsh

R/W

SCK

MOSI

MISO

Tssd

Tco

Tss

Tck TchTcl

Tssz

Figure 3 Serial peripheral interface timing

AX5051 Datasheet(PDF) 32 Page - ON Semiconductor