AX5051 datasheet(39/44 Pages) ONSEMI

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Application Information

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AX5051

7.2. Antenna Interface Circuitry

The ANTP and ANTN pins provide RF input to the LNA when AX5051 is in receiving

mode, and RF output from the PA when AX5051 is in transmitting mode. A small

antenna can be connected with an optional translation network.

The network must

provide DC power to the PA and LNA. A biasing to VREG is necessary.

Beside biasing and impedance matching, the proposed networks also provide low pass

filtering to limit spurious emission.

Single-Ended Antenna Interface

CC1

CB1

LT2

single-

ended

equipment

or antenna

IC Antenna

Pins

VREG

LT1

LC2

LC1

CM1

LB1

CB2

LB2

CF1

CF2

LF1

CT1

CT2

CC2

CM2

Optional filter

stage to suppress

TX harmonics

Figure 5 Structure of the antenna interface to 50  single-ended equipment or antenna

Frequency

Band

LC1,2

[nH]

CC1,2

[pF]

LT1,2

[nH]

CT1,2

[pF]

CM1,2

[pF]

LB1,2

[nH]

CB1,2

[pF]

LF1

[nH]

CF1,2

[pF]

868 / 915

MHz

0.9

2.4

2.7

OHM

N.C.

433 MHz

120

2.2

7.5

6.0

5.2

OHM

N.C

7.3. Voltage Regulator

The AX5051 has an integrated voltage regulator, which generates a stable supply

voltage VREG from the voltage applied at VDD_IO. Use VREG to supply all the VDD

supply pins.

AX5051 Datasheet(PDF) 39 Page - ON Semiconductor

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