MT9044AP datasheet(4/30 Pages) MITEL

4 / 30 page

MT9044

Advance Information

LOS1

Primary Reference Loss (TTL Input). Typically, external equipment applies a

logic high to this input when the PRI reference signal is lost or invalid. The logic

level at this input is gated in by the rising edge of F8o. See LOS2 description. This

pin is internally pulled down to VSS.

TDO

Test Serial Data Out (TTL Output). JTAG serial data is output on this pin on the

falling edge of TCK. This pin is held in high impedance state when JTAG scan is

not enable.

MS2

Mode/Control Select 2 (TTL Input). This input, in conjunction with MS1,

determines the device’s mode (Automatic or Manual) and state (Normal, Holdover

or Freerun) of operation. The logic level at this input is gated in by the rising edge

of F8o. See Table 3.

MS1

Mode/Control Select 1 (TTL Input).

The logic level at this input is gated in by the

rising edge of F8o. See pin description for MS2. This pin is internally pulled down

to VSS.

RSEL

Reference Source Select (TTL Input). In Manual Control, a logic low selects the

PRI (primary) reference source as the input reference signal and a logic high

selects the SEC (secondary) input. In Automatic Control, this pin must be at logic

low. The logic level at this input is gated in by the rising edge of F8o. See Table 2.

This pin is internally pulled down to VSS.

TEST

Test (TTL Input). This input is normally tied low. When pulled high, it enables

internal test modes. This pin is internally pulled down to VSS.

FS2

Frequency Select 2 (TTL Input). This input, in conjunction with FS1, selects

which of three possible frequencies (8kHz, 1.544MHz, or 2.048MHz) may be input

to the PRI and SEC inputs. See Table 1.

FS1

Frequency Select 1 (TTL Input). See pin description for FS2.

TDI

Test Serial Data In (TTL Input). JTAG serial test instructions and data are shifted

in on this pin. This pin is internally pulled up to VDD.

RST

Reset (Schmitt Input). A logic low at this input resets the MT9044. To ensure

proper operation, the device must be reset after changes to the method of control,

reference signal frequency changes and power-up. The RST pin should be held

low for a minimum of 300ns. While the RST pin is low, all frame and clock outputs

are at logic high. Following a reset, the input reference source and output clocks

and frame pulses are phase aligned as shown in Figure 19.

TMS

Test Mode Select (TTL Input). JTAG signal that controls the state transitions of

the TAP controller. This pin is internally pulled up to VDD.

Pin Description (continued)

Pin #

PLCC

Pin #

MQFP

Name

Description

MT9044AP Datasheet(PDF) 4 Page - Mitel Networks Corporation

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