MT9044AP datasheet(5/30 Pages) MITEL

5 / 30 page

Advance Information

MT9044

Functional Description

The MT9044 is a Multitrunk System Synchronizer,

providing timing (clock) and synchronization (frame)

signals to interface circuits for T1 and E1 Primary

Rate Digital Transmission links.

Figure 1 shows the functional block diagram which is

described in the following sections.

Reference Select MUX Circuit

The MT9044 accepts two simultaneous reference

input signals and operates on their falling edges.

Either the primary reference (PRI) signal or the

secondary reference (SEC) signal can be selected

as input to the TIE Corrector Circuit. The selection is

based

the

Control,

Mode

and

Reference

Selection of the device. See Tables 1, 4 and 5.

Frequency Select MUX Circuit

The MT9044 operates with one of three possible

input reference frequencies (8kHz, 1.544MHz or

2.048MHz). The frequency select inputs (FS1 and

FS2) determine which of the three frequencies may

be used at the reference inputs (PRI and SEC). Both

inputs must have the same frequency applied to

them. A reset (RST) must be performed after every

frequency select input change. Operation with FS1

and FS2 both at logic low is reserved and must not

be used. See Table 1.

Table 1 - Input Frequency Selection

Time Interval Error (TIE) Corrector Circuit

The TIE corrector circuit, when enabled, prevents a

step change in phase on the input reference signals

(PRI or SEC) from causing a step change in phase at

the input of the DPLL block of Figure 1.

During reference input rearrangement, such as

during a switch from the primary reference (PRI) to

the secondary reference (SEC), a step change in

phase on the output signals will occur. A phase step

at the input of the DPLL will lead to unacceptable

phase changes in the output signal.

As shown in Figure 3, the TIE Corrector Circuit

receives one of the two reference (PRI or SEC)

signals, passes the signal through a programmable

delay line, and uses this delayed signal as an

internal virtual reference, which is input to the DPLL.

Therefore, the virtual reference is a delayed version

of the selected reference.

During a switch, from one reference to the other, the

State Machine ﬁrst changes the mode of the device

FS2

FS1

Input Frequency

Reserved

8kHz

1.544MHz

2.048MHz

Figure 3 - TIE Corrector Circuit

Programmable

Delay Circuit

Control Signal

Delay Value

TCLR

Resets Delay

Compare

Circuit

TIE Corrector

Enable

from

State Machine

Control

Circuit

Feedback

Signal from

Frequency

Select MUX

PRI or SEC

from

Reference

Select Mux

Virtual

Reference

to DPLL

MT9044AP Datasheet(PDF) 5 Page - Mitel Networks Corporation

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