MT9044AP datasheet(6/30 Pages) MITEL

6 / 30 page

MT9044

Advance Information

from Normal to Holdover.

In Holdover Mode, the

DPLL no longer uses the virtual reference signal, but

generates an accurate clock signal using storage

techniques. The Compare Circuit then measures the

phase delay between the current phase (feedback

signal) and the phase of the new reference signal.

This delay value is passed to the Programmable

Delay Circuit (See Figure 3).

The new virtual

reference signal is now at the same phase position

as the previous reference signal would have been if

the reference switch had not taken place. The State

Machine then returns the device to Normal Mode.

The DPLL now uses the new virtual reference signal,

and since no phase step took place at the input of

the DPLL, no phase step occurs at the output of the

DPLL. In other words, reference switching will not

create a phase change at the input of the DPLL, or at

the output of the DPLL.

Since internal delay circuitry maintains the alignment

between the old virtual reference and the new virtual

reference, a phase error may exist between the

selected input reference signal and the output signal

of the DPLL. This phase error is a function of the

difference in phase between the two input reference

signals during reference rearrangements. Each time

a reference switch is made, the delay between input

signal and output signal will change. The value of

this delay is the accumulation of the error measured

during each reference switch.

The programmable delay circuit can be zeroed by

applying a logic low pulse to the TIE Circuit Reset

(TCLR) pin. A minimum reset pulse width is 300ns.

This results in a phase alignment between the input

reference signal and the output signal as shown in

Figure 20.

The speed of the phase alignment

correction

limited

5ns

per

125us,

and

convergence is in the direction of least phase travel.

The state diagrams of Figure 7 and 8 indicate the

state changes that activate the TIE Corrector Circuit.

Digital Phase Lock Loop (DPLL)

As shown in Figure 4, the DPLL of the MT9044

consists of a Phase Detector, Limiter, Loop Filter,

Digitally Controlled Oscillator, and a Control Circuit.

Phase Detector - the Phase Detector compares the

virtual reference signal from the TIE Corrector circuit

with the feedback signal from the Frequency Select

MUX

circuit,

and

provides

error

signal

corresponding to the phase difference between the

two. This error signal is passed to the Limiter circuit.

The Frequency Select MUX allows the proper

feedback signal to be externally selected (e.g., 8kHz,

1.544MHz or 2.048MHz).

Limiter - the Limiter receives the error signal from

the Phase Detector and ensures that the DPLL

responds to all input transient conditions with a

maximum output phase slope of 5ns per 125us. This

is well within the maximum phase slope of 7.6ns per

125us or 81ns per 1.326ms speciﬁed by AT&T

TR62411, and Bellcore GR-1244-CORE.

Loop Filter - the Loop Filter is similar to a ﬁrst order

low pass ﬁlter with a 1.9 Hz cutoff frequency for all

three

reference

frequency

selections

(8kHz,

1.544MHz or 2.048MHz). This ﬁlter ensures that the

jitter transfer requirements in ETS 300 011 and AT&T

TR62411 are met.

Control Circuit - the Control Circuit uses status and

control information from the State Machine and the

Input Impairment Circuit to set the mode of the

DPLL.

The three possible modes are Normal,

Holdover and Freerun.

Digitally Controlled Oscillator (DCO) - the DCO

receives the limited and ﬁltered signal from the Loop

FIlter,

and

based

its

value,

generates

corresponding

digital

output

signal.

The

synchronization method of the DCO is dependent on

the state of the MT9044.

Figure 4 - DPLL Block Diagram

Limiter

Loop Filter

Digitally

Controlled

Oscillator

Phase

Detector

Feedback Signal from

Frequency Select MUX

State Select from

Input Impairment

Monitor

State Select from

State Machine

DPLL Reference to

Output Interface Circuit

Virtual Reference from

TIE Corrector

Control

Circuit

MT9044AP Datasheet(PDF) 6 Page - Mitel Networks Corporation

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