MT9074AP datasheet(13/122 Pages) MITEL

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Advance Information

MT9074

Figure 11- TR 62411 Jitter Attenuation Curve

-0.5

19.5

400

10K

-20 dB/decade

Frequency (Hz)

Phase Lock Loop (PLL)

The MT9074 contains a PLL, which can be locked to

either an input 4.096 Mhz clock or the extracted line

clock.The PLL will attenuate jitter from less than

2.5 Hz and roll-off at a rate of 20 dB/decade. Its

intrinsic jitter is less than 0.02 UI. The PLL will meet

the jitter transfer characteristics as speciﬁed by ATT

document

62411

and

the

relevant

recommendations as shown in Figure 11.

Clock Jitter Attenuation Modes

MT9074 has three basic jitter attenuation modes of

operation, selected by the BS/LS and S/FR control

pins. Referring to the mode names given in Table 5

the basic operation of the jitter attenuation modes

are:

•

System Bus Synchronous Mode.

•

Line Synchronous Mode.

•

Free-run mode.

In System Bus Synchronous mode pins C4b and F0b

are always conﬁgured as inputs, while in the Line

Synchronous and Free-Run modes C4b and F0b are

conﬁgured as outputs.

System Bus Synchronous mode an external clock

is applied to C4b. The applied clock is dejittered by

the internal PLL before being used to synchronize

the transmitted data. The clock extracted (with no

jitter attenuation performed) from the receive data

can be monitored on pin E1.5o.

Line Synchronous mode, the clock extracted from

the receive data is dejittered using the internal PLL

and then output on pin C4b. Pin E1.5o provides the

extracted receive clock before it has been dejittered.

The transmit data is synchronous to the clean

receive clock.

Free-Run mode the transmit data is synchronized

to the internally generated clock. The internal clock

is output on pin C4b. The clock signal extracted from

the receive data is not dejittered and is output

directly on E1.5o.

Depending on the mode selection above, the PLL

can either attenuate transmit clock jitter or the

receive clock jitter. Table 5 shows the appropriate

conﬁguration of each control pin to achieve the

Mode Name

BS/LS

S/FR

Note

System Bus

Synchronous

PLL locked to C4b.

Line Synchronous

PLL locked to E1.5o.

Free-Run

PLL free - running.

Table 5 - Selection of clock jitter attenuation

modes using the M/S and MS/FR pins

MT9074AP Datasheet(PDF) 13 Page - Mitel Networks Corporation

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