MT9074AP datasheet(35/122 Pages) MITEL

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Advance Information

MT9074

Associated with each counter is a maskable event

occurrence

interrupt

and

maskable

counter

overﬂow interrupt. Overﬂow interrupts are useful

when cumulative error counts are being recorded.

For example, every time the framing bit error counter

overﬂow interrupt (FERO) occurs, 256 frame errors

have been received since the last FERO (page 04H,

address 1DH)interrupt. All counters are cleared and

held low by programming the counter clear bit -

CNTCLR - high (bit 4 of the Reset Control Word,

page 1H, address 1AH). An alternative approach to

event reporting is to mask error events and to enable

the 1 second sample bit (SAMPLE - bit 3 of the

Reset Control Word). When this bit is set the

counters for change of frame alignment, loss of

frame alignment, bpv errors, crc errors, errored

framing bits, and multiframes out of sync are

updated on one second intervals coincident with the

maskable one second interrupt timer.

In E1 mode, MT9074 has six error counters, which

can be used for maintenance testing, an ongoing

measure of the quality of a PCM 30 link and to assist

the designer in meeting speciﬁcations such as ITU-T

I.431 and G.821. All counters can be preset or

cleared by writing to the appropriate locations.

Associated with each counter is a maskable event

occurrence

interrupt

and

maskable

counter

overﬂow interrupt. Overﬂow interrupts are useful

when cumulative error counts are being recorded.

For example, every time the frame error counter

overﬂow (FERO) interrupt occurs, 256 frame errors

have been received since the last FERO interrupt. All

counters are cleared and held low by programming

the counter clear bit (master control page 01H,

address 1A, bit 4) high. Counter overﬂows set bits in

the counter overﬂow latch (page 04H, address 1FH);

this latch is cleared when read.

The overﬂow reporting latch (page 04H, address

1FH) contains a register whose bits are set when

individual counters overﬂow. These bits stay high

until the register is read.

T1 Counters

Framing Bit Error Counter (FC7-0)

This eight bit counter counts errors in the framing

pattern. In ESF mode any error in the 001011

framing pattern increments the counter. In SLC-96

mode any error in the Ft bit position is counted. In D4

mode Ft errors are always counted, Fs bits (except

for the Sbit in frame 12) may optionally be counted (if

control bit FSI is set high - page 1H, address 10H, bit

2). The counter is located on page 4H, address 13H.

There are two maskable interrupts associated with

the Framing bit error measurement. A single error

may generate an interrupt (enable by setting FERI

high - bit 7 of the Interrupt Mask Word One, page 1H,

address 1CH). A counter overﬂow interrupt may be

enabled by setting control bit FEOM high - bit 2 of

Interrupt Mask Word Two (page 1H, address 1DH).

Out Of Frame / Change Of Frame Alignment

Counter (OOF3-0/COFA3-0)

This register space is shared by two nibbles. One is

the count of out of frame events. The other

independent counter is incremented when, after a

resynchronization, the frame alignment has moved.

This count is reported in page 4, address 13H.

There are two interrupts associated with the Change

of Frame Alignment counter. A single error may

generate an interrupt (enable by setting COFAI high -

bit 4 of the Interrupt Mask Word One, page 1H,

address 1CH). A counter overﬂow interrupt may be

enabled by setting control bit COFAO high - bit 4 of

Interrupt Mask Word Two (page 1H, address 1DH).

There is one interrupt associated with the Out of

Frame counter. A counter overﬂow interrupt may be

enabled by setting control bit OOFO high - bit 5 of

Interrupt Mask Word Two (page 1H, address 1DH).

Multiframes out of Sync Counter (MFOOF7-

MFOOF0)

This eight bit counter MFOOF7 - MFOOF0 is located

on page 4 address 15H, and is incremented once per

multiframe (1.5 ms for D4 and 3 ms for ESF) during

the time that the framer is out of terminal frame

synchronization.

There is a maskable interrupt associated with the

measurement. A counter overﬂow interrupt may be

enabled by setting control bit MFOOFO high - bit 1 of

Interrupt Mask Word Two (page 1H, address 1DH).

CRC-6 Error Counter (CC15-0)

CRC-6 errors are recorded by this counter for ESF

links. This 16 bit counter is located on page 4H,

addresses 18H and 19H.

There are two maskable interrupts associated with

the CRC error measurement. A single error may

generate an interrupt (enable by setting CRCI high -

bit 6 of the Interrupt Mask Word One, page 1H,

address 1CH). A counter overﬂow interrupt may be

enabled by setting control bit CRCO high - bit 6 of

Interrupt Mask Word Two (page 1H, address 1DH).

MT9074AP Datasheet(PDF) 35 Page - Mitel Networks Corporation

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