MT9074AP datasheet(3/122 Pages) MITEL

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Advance Information

MT9074

Pin Description

Pin #

Name

Description

68 Pin

PLCC

100 Pin

MQFP

OSC1

Oscillator Input. This pin is either connected via a 20.000 MHz crystal to OSC2

where a crystal is used, or is directly driven when a 20.000 MHz. oscillator is

employed.

OSC2

Oscillator Output. Connect a 20.0 MHz crystal between OSC1 and OSC2. Not

suitable for driving other devices.

368

VSS

Negative Power Supply (Input). Digital ground.

469

VDD

Positive Power Supply (Input). Digital supply (+5V

± 5%).

CSTo

Control ST-BUS Output. CSTo carries serial streams for CAS and CCS

respectively a 2.048 Mbit/s ST-BUS status stream which contains the 30 receive

signalling nibbles (ABCDZZZZ or ZZZZABCD). The most signiﬁcant nibbles of

each ST-BUS time slot are valid and the least signiﬁcant nibbles of each ST-BUS

time slot are tristated when control bit MSN (page 01H, address 1AH, bit 1) is set

to 1. If MSN=0, the position of the valid and tristated nibbles are reversed.

CSTi

Control ST-BUS Input. CSTi carries serial streams for CAS and CCS respectively

a 2.048 Mbit/s ST-BUS control stream which contains the 30 transmit signalling

nibbles (ABCDXXXX or XXXXABCD) when RPSIG=0. When RPSIG=1 this pin

has no function. The most signiﬁcant nibbles of each ST-BUS time slot are valid

and the least signiﬁcant nibbles of each ST-BUS time slot are ignored when control

bit MSN (page 01H, address 1AH, bit 1) is set to 1. If MSN=0, the position of the

valid and ignored nibbles is reversed.

DSTo

Data ST-BUS Output. A 2.048 Mbit/s serial stream which contains the 24/30

PCM(T1/E1) or data channels received on the PCM 24/30 (T1/E1) line.

DSTi

Data ST-BUS Input. A 2.048 Mbit/s serial stream which contains the 24/30 (T1/

E1)PCM or data channels to be transmitted on the PCM 24/30 (T1/E1)line.

974

DS/RD

Data/Read Strobe (Input).

In Motorola mode (DS), this input is the active low data strobe of the

microprocessor interface.

In Intel mode (RD), this input is the active low read strobe of the microprocessor

interface.

Chip Select (Input). This active low input enables the non-multiplexed parallel

microprocessor interface of the MT9074. When CS is set to high, the

microprocessor interface is idle and all bus I/O pins will be in a high impedance

state.

RESET

RESET (Input). This active low input puts the MT9074 in a reset condition. RESET

should be set to high for normal operation. The MT9074 should be reset after

power-up. The RESET pin must be held low for a minimum of 1

µsec. to reset the

device properly.

IRQ

Interrupt Request (Output). A low on this output pin indicates that an interrupt

request is presented. IRQ is an open drain output that should be connected to VDD

through a pull-up resistor. An active low CS signal is not required for this pin to

function.

13 -

86-89

D0 - D3

Data 0 to Data 3 (Three-state I/O). These signals combined with D4-D7 form the

bidirectional data bus of the microprocessor interface (D0 is the least signiﬁcant

bit).

MT9074AP Datasheet(PDF) 3 Page - Mitel Networks Corporation

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