MT9074AP datasheet(4/122 Pages) MITEL

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MT9074

Advance Information

Vss

Negative Power Supply (Input). Digital ground.

Internal Connection. Tie to Vss (ground) for normal operation.

INT/MOT

Intel/Motorola Mode Selection (Input).A high on this pin conﬁgures the

processor interface for the Intel parallel non-multiplexed bus type. A low conﬁgures

the processor interface for the Motorola parallel non-multiplexed type.

VDD

Positive Power Supply (Input). Digital supply (+5V

± 5%).

21 -

94-97

D4 - D7

Data 4 to Data 7 (Three-state I/O). These signals combined with D0-D3 form the

bidirectional data bus of the parallel processor interface (D7 is the most signiﬁcant

bit).

R/W/WR

Read/Write/Write Strobe (Input). In Motorola mode (R/W), this input controls the

direction of the data bus D[0:7] during a microprocessor access. When R/W is

high, the parallel processor is reading data from the MT9074. When low, the

parallel processor is writing data to the MT9074. For Intel mode (WR), this active

low write strobe conﬁgures the data bus lines as output.

26 -

99, 8-11

AC0 - AC4 Address/Control 0 to 4 (Inputs). Address and control inputs for the non-

multiplexed parallel processor interface. AC0 is the least signiﬁcant input.

GNDARx

Receive Analog Ground (Input). Analog ground for the LIU receiver.

RTIP

RRING

Receive TIP and RING (Input). Differential inputs for the receive line signal - must

be transformer coupled (See Figure 5). In digital framer mode these are TTL level

inputs that connect to the digital outputs of a receiver. If the receiver serial data

output is NRZ connect that output to RTIP. If the receiver data output is split phase

unipolar signal connect one signal to RTIP and the complementary signal to

RRING.

VDDARx

Receive Analog Power Supply (Input). Analog supply for the LIU receiver (+5V

5%).

VDD

Positive Power Supply (Input). Digital supply (+5V

± 5%).

VSS

Negative Power Supply (Input). Digital ground.

TxA

Transmit A (Output). When the internal LIU is disabled (digital framer only

mode), if control bit NRZ=1, and NRZ output data is clocked out on pin TxA with

the rising edge of C1.50 (TxB has no function when NRZ format is selected). If

NRZ=0, pins TxA and TxB are a complementary pair of signals that output digital

dual-rail clocked out with the rising edge of C1.50.

TxB

Transmit B (Output). When the internal LIU is disabled and control bit NRZ=0,

pins TxA and TxB are a complementary pair of signals that output digital dual-rail

data clocked out with the rising edge of C1.50.

RxDLCLK Data Link Clock (Output). A gapped clock signal derived from the extracted clock

from the line clock, available for an external device to clock in RxDL data (at 4, 8,

12, 16 or 20 kHz) on the rising edge.

RxDL

Receive Data Link (Output). A serial bit stream containing received line data after

zero code suppression. This data is clocked out with the rising edge of E1.5o.

TxMF

Transmit Multiframe Boundary (Input). An active low input used to set the

transmit multiframe boundary (CAS or CRC multiframe). The MT9074 will generate

its own multiframe if this pin is held high. This input is usually pulled high for most

applications.

Pin Description

Pin #

Name

Description

68 Pin

PLCC

100 Pin

MQFP

MT9074AP Datasheet(PDF) 4 Page - Mitel Networks Corporation

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