MT9160

Preliminary Information

7-78

Figure 2 - Pin Connections

Pin Description

Pin #

SOIC

DIP

Name

Description

11

22

3

4

PWRST

Power-up Reset (Input). CMOS compatible input with Schmitt Trigger (active low).

45

IC

56

A/

µ/IRQ A/µ - When internal control bit DEn = 0 this CMOS level compatible input pin governs

the companding law used by the filter/Codec;

µ-Law when tied to V

IRQ - When internal control bit DEn = 1 this pin becomes an open-drain interrupt

output signalling valid access to the D-Channel registers in ST-BUS mode.

67

Digital Ground. Nominally 0 volts.

78

CS

Chip Select (Input).

This input signal is used to select the device for microport data

transfers. Active low. TTL level compatible.

810SCLK

Serial Port Synchronous Clock (Input). Data clock for microport. TTL level

compatible.

911

DATA 1

Bidirectional Serial Data. Port for microprocessor serial data transfer. In Motorola/

National mode of operation, this pin becomes the data transmit pin only and data

receive is performed on the DATA 2 pin. Input TTL level compatible.

10

12

DATA 2

Serial Data Receive. In Motorola/National mode of operation, this pin is used for

data receive. In Intel mode, serial data transmit and receive are performed on the

DATA 1 pin and DATA 2 is disconnected. Input TTL level compatible.

24 PIN PDIP

M -

M +

VBias

VRef

IC

VSSD

SCLK

DATA1

DATA2

Din

Dout

VSSA

HSPKR +

HSPKR -

VDD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

24

23

22

21

20

19

18

17

NC

PWRST

A/

µ/IRQ

CS

NC

STB/F0i

NC

CLOCKin

NC

M -

M +

VBias

VRef

IC

VSSD

SCLK

DATA1

DATA2

Din

Dout

VSSA

HSPKR +

HSPKR -

VDD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

20

19

18

17

PWRST

A/

µ/IRQ

CS

STB/F0i

CLOCKin

20 PIN SOIC