Preliminary Information

MT9160

7-79

11

13

Data Output. A high impedance three-state digital output for 8 bit wide channel data

being sent to the Layer 1 transceiver. Data is shifted out via this pin concurrent with

the rising edge of the bit clock during the timeslot defined by STB, or according to

standard ST-BUS timing.

12

14

Data Input. A digital input for 8 bit wide channel data received from the Layer 1

transceiver. Data is sampled on the falling edge of the bit clock during the timeslot

defined by STB, or according to standard ST-BUS timing. Input level is CMOS

compatible.

13

15

STB/F0i

Data Strobe/Frame Pulse (Input). For SSI mode this input determines the 8 bit

timeslot used by the device for both transmit and receive data. This active high signal

has a repetition rate of 8 kHz. Standard frame pulse definitions apply in ST-BUS

mode (refer to Figure 11). CMOS level compatible input.

14

17

CLOCKin Clock (Input). (CMOS level compatible). The clock provided to this input pin is used

for the internal device functions. For SSI mode connect the bit clock to this pin when

it is 512 kHz or greater. Connect a 4096 kHz clock to this input when the available bit

clock is 128 kHz or 256 kHz. For ST-BUS mode connect C4i to this pin.

15

18

Positive Power Supply (Input). Nominally 5 volts.

16

19

HSPKR-

Inverting Handset Speaker (Output). Output to the handset speaker (balanced).

17

20

HSPKR+ Non-Inverting Handset Speaker (Output). Output to the handset speaker

(balanced).

18

22

Analog Ground (Input). Nominally 0 volts.

19

23

M-

Inverting Microphone (Input). Inverting input to microphone amplifier from the

handset microphone.

20

24

M+

Non-Inverting Microphone (Input). Non-inverting input to microphone amplifier

from the handset microphone.

3,9,

16,21

NC

No Connect. (DIP Package only).

Pin Description (continued)

Pin #

SOIC

DIP

Name

Description