MT9162AS datasheet(2/17 Pages) MITEL

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MT9162

Advance Information

7-162

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

1VBias

Bias Voltage (Output). (VDD/2) volts is available at this pin for biasing external ampliﬁers.

Connect 0.1

µ F capacitor to V

SS. Connect 1 µF capacitor to Vref.

2VRef

Reference Voltage for Codec (Output). Nominally [(VDD/2)-1.9] volts. Used internally.

Connect 0.1

µ F capacitor to V

SS. Connect 1 µF capacitor to VBias

PWRST Power-up Reset. Resets internal state of device via Schmitt Trigger input (active low).

4IC

Internal Connection. Tie externally to VSS for normal operation.

5A/

µ Law Selection. CMOS level compatable input pin governs the companding law used by

the device. A-law selected when pin tied to VDD or µ-law selected when pin tied to VSS.

RXMute Receive Mute. When 1, the transmit PCM is forced to negative zero code. When 0, normal

operation. CMOS level compatible.

TXMute Transmit Mute. When 1, the transmit PCM is forced to negative zero code. When 0, normal

operation. CMOS level compatible.

CSL0

CSL1

CSL2

Clock Speed Select. These pins are used to program the speed of the SSI mode as well as

the conversion rate between the externally supplied MCL clock and the 512 kHz clock required

by the ﬁlter/codec. Refer to Table 2 for details. CMOS level compatible.

Dout

Data Output. A tri-state digital output for 8-bit wide channel data being sent to the Layer 1

device. Data is shifted out via the pin concurrent with the rising edge of BCL during the timeslot

deﬁned by STB.

Din

Data Input. A digital input for 8-bit wide data from the layer 1 device. Data is sampled on the

falling edge of BCL during the timeslot deﬁned by STB. CMOS level compatible.

STB

Data Strobe. This input determines the 8-bit timeslot used by the device for both transmit and

receive data. This active high signal has a repetition rate of 8 kHz. CMOS level compatible.

CLOCKin Clock (Input). The clock provided to this input pin is used by the internal device functions.

Connect bit clock to this pin when it is 512 kHz or greater. Connect a 4096 kHz clock to this pin

when the bit clock is 128 kHz or 256 kHz. CMOS level compatible.

VDD

Positive Power Supply. Nominally 5 volts.

AOUT-

Inverting Analog Output. (balanced).

AOUT+

Non-Inverting Analog Output. (balanced).

VSS

Ground. Nominally 0 volts.

Ain-

Inverting Analog Input. No external anti-aliasing is required.

Ain+

Non-Inverting Analog Input. Non-inverting input. No external anti-aliasing is required.

AIN-

AIN+

VBias

VRef

RXMUTE

CSL0

CSL1

CSL2

Din

Dout

VSS

AOUT +

AOUT -

VDD

PWRST

TXMUTE

STB

CLOCKin

20 PIN PDIP/SOIC/SSOP

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