MT9162AS datasheet(3/17 Pages) MITEL

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Advance Information

MT9162

7-163

Overview

The 5V single rail Codec features complete Analog/

Digital

and

Digital/Analog

conversion

audio

signals (Filter/Codec) and an analog interface to a

standard analog transmitter and receiver (Analog

Interface). The receiver ampliﬁer is capable of

driving a 20k ohm load.

Functional Description

Filter/Codec

The Filter/Codec block implements conversion of the

analog 0-3.3 kHz speech signals to/from the digital

domain compatible with 64 kb/s PCM B-Channels.

Selection of companding curves and digital code

assignment are programmable. These are ITU-T

G.711 A-law or

µ-Law, with true-sign/Alternate Digit

Inversion.

The Filter/Codec block also implements a transmit

audio path gain in the analog domain.

Figure 3

depicts the nominal half-channel for the MT9162.

The internal architecture is fully differential to provide

the best possible noise rejection as well as to allow a

wide dynamic range from a single 5 volt supply

design.

This

fully

differential

architecture

continued into the analog interface section to provide

full chip realization of these capabilities for the

external functions.

A reference voltage (VRef), for the conversion

requirements of the Codec section, and a bias

voltage (VBias), for biasing the internal analog

sections, are both generated on-chip. VBias is also

brought to an external pin so that it may be used for

biasing external gain setting ampliﬁers. A 0.1

µF

capacitor must be connected from VBias to analog

ground at all times. Likewise, although VRef may only

be used internally, a 0.1

µF capacitor from the V

Ref

pin to ground is required at all times. The analog

ground reference point for these two capacitors must

be physically the same point. To facilitate this the

VRef and VBias pins are situated on adjacent pins.

The transmit ﬁlter is designed to meet ITU-T G.714

speciﬁcations. An anti-aliasing ﬁlter is included. This

is a second order lowpass implementation with a

corner frequency at 25 kHz.

The receive ﬁlter is designed to meet ITU-T G.714

speciﬁcations.

Filter

response

peaked

compensate for the sinx/x attenuation caused by the

8 kHz sampling rate.

Companding law selection for the Filter/Codec is

provided by the A/

µ companding control pin. Table

1 illustrates these choices.

Table 1: Law Selection

Analog Interfaces

Standard interfaces are provided by the MT9162.

These are:

• The analog inputs (transmitter), pins AIN+/AIN-.

The maximum peak to peak input is 3.667Vpp

µ−law and across AIN+/AIN- 3.8Vpp A-law.

• The analog outputs (receiver), pins AOUT+/

AOUT-. This

internally

compensated

fully

differential output driver is capable of driving a

load of 20k ohms.

PCM Serial Interface

A serial link is required to transport data between the

MT9162 and an external digital transmission device.

The MT9162 utilizes the strobed data interface found

on many standard Codec devices. This interface is

commonly referred to as Simple Serial Interface

(SSI).

The required mode of operation is selected via the

CSL2-0 control pins.

See Table 2 for selections

based in CSL2-0 pin settings.

Quiet Code

The PCM serial port can be made to send quiet code

to the decoder and receive ﬁlter path by setting the

RxMute pin high. Likewise, the PCM serial port will

send quiet code in the transmit path when the

Code

ITU-T (G.711)

µ -Law

A-Law

+ Full Scale

1000 0000

1010 1010

+ Zero

1111 1111

1101 0101

-Zero

(quiet code)

0111 1111

0101 0101

- Full Scale

0000 0000

0010 1010

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