15

9, 16

11

10

12

13

14

IN-

IN+

RDY

RST

10k

10k

FLT

0.1F

GND1

2.25V-5.5V

10R

ISO5452



C

15

9, 16

11

10

12

13

14

IN-

IN+

RDY

RST

10k

10k

FLT

0.1F

GND1

2.25V-5.5V

10R

ISO5452



C

ISO5452

SLLSEQ4A – AUGUST 2015 – REVISED SEPTEMBER 2015

www.ti.com

10.2.2.6 Auto-Reset

In this case, the gate control signal at IN+ is also applied to the RST input to reset the fault latch every switching

cycle. Incorrect RST makes output go low. A fault condition, however, the gate driver remains in the latched fault

state until the gate control signal changes to the 'gate low' state and resets the fault latch.

If the gate control signal is a continuous PWM signal, the fault latch will always be reset before IN+ goes high

again. This configuration protects the IGBT on a cycle by cycle basis and automatically resets before the next

'on' cycle.

Figure 53. Auto Reset for Non-inverting and Inverting Input Configuration

10.2.2.7 DESAT Pin Protection

Switching inductive loads causes large instantaneous forward voltage transients across the freewheeling diodes

of IGBTs. These transients result in large negative voltage spikes on the DESAT pin which draw substantial

current out of the device. To limit this current below damaging levels, a 100-

Ω to 1-kΩ resistor is connected in

series with the DESAT diode.

Further protection is possible through an optional Schottky diode, whose low forward voltage assures clamping of

the DESAT input to GND2 potential at low voltage levels.

26

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