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ISO5452 Datasheet(PDF) 30 Page - Texas Instruments |
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ISO5452 Datasheet(HTML) 30 Page - Texas Instruments |
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30 / 37 page ![]() 10 mils 10 mils 40 mils FR-4 r ~ 4.5 Keep this space free from planes, traces, pads, and vias Ground plane Power plane Low-speed traces High-speed traces ISO5452 SLLSEQ4A – AUGUST 2015 – REVISED SEPTEMBER 2015 www.ti.com 11 Power Supply Recommendations To ensure reliable operation at all data rates and supply voltages, a 0.1- μF bypass capacitor is recommended at input supply pin VCC1 and 1-μF bypass capacitor is recommended at output supply pin VCC2. The capacitors should be placed as close to the supply pins as possible. Recommended placement of capacitors needs to be 2-mm maximum from input and output power supply pin (VCC1 and VCC2). 12 Layout 12.1 Layout Guidelines A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 59). Layer stacking should be in the following order (top-to-bottom): high-current or sensitive signal layer, ground plane, power plane and low-frequency signal layer. • Routing the high-current or sensitive traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the gate driver and the microcontroller and power transistors. Gate driver control input, Gate driver output OUTH/L and DESAT should be routed in the top layer. • Placing a solid ground plane next to the sensitive signal layer provides an excellent low-inductance path for the return current flow. On the driver side, use GND2 as the ground plane. • Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pF/inch2. On the gate-driver VEE2 and VCC2 can be used as power planes. They can share the same layer on the PCB as long as they are not connected together. • Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias. For more detailed layout recommendations, including placement of capacitors, impact of vias, reference planes, routing etc. see Application Note SLLA284, Digital Isolator Design Guide. 12.2 PCB Material Standard FR-4 epoxy-glass is recommended as PCB material. FR-4 (Flame Retardant 4) meets the requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its self- extinguishing flammability-characteristics. 12.3 Layout Example Figure 59. Recommended Layer Stack 30 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO5452 |
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